Abstract: Eliminating or reducing an operand line crossing penalty by performing an initial fetch for an operand from a data cache of a processor. The initial fetch is performed by allowing or permitting the initial fetch to occur unaligned with reference to a quadword boundary. A plurality of subsequent fetches for a corresponding plurality of operands from the data cache are performed wherein each of the plurality of subsequent fetches is aligned to any of a plurality of quadword boundaries to prevent each of a plurality of individual fetch requests from spanning a plurality of lines in the data cache. A steady stream of data is maintained by placing an operand buffer at an output of the data cache to store and merge data from the initial fetch and the plurality of subsequent fetches, and to return the stored and merged data to the processor.

Abstract: A method for processor error checking including receiving an instruction data, generating a pre-processing parity data based on the instruction data, maintaining the pre-processing parity data, processing the instruction data, generating a post-processing parity data based on the processed instruction data, checking for an error related to processing the instruction data by comparing the post-processing parity data to the pre-processing parity data, and transmitting an error signal that indicates the error related to processing the instruction data occurred if the post-processing parity data does not match the pre-processing parity data, wherein checking for the error related to processing the instruction data is performed without using a duplicate processing circuitry.

Abstract: A pipelined processor including an architecture for address generation interlocking, the processor including: an instruction grouping unit to detect a read-after-write dependency and to resolve instruction interdependency; an instruction dispatch unit (IDU) including address generation interlock (AGI) and operand fetching logic for dispatching an instruction to at least one of a load store unit and an execution unit; wherein the load store unit is configured with access to a data cache and to return fetched data to the execution unit; wherein the execution unit is configured to write data into a general purpose register bank; and wherein the architecture provides support for bypassing of results of a load multiple instruction for address generation while such instruction is executing in the execution unit before the general purpose register bank is written. A method and a computer system are also provided.

Abstract: A pipelined microprocessor configured for long operand instructions is disclosed. The microprocessor includes a memory unit and a load-store unit. The load store unit is coupled to the memory unit and includes a data formatter receiving information from the memory unit and including an operand selector and a shift register portion. The microprocessor also includes an execution unit coupled to the load-store unit and receiving operand information there from. The execution unit includes output latches coupled to a storage location within the execution unit for storing output information from the execution unit.

Abstract: System, method and computer program products for failure analysis implementing automated comparison of multiple reference models. An exemplary embodiment includes a method for failure analysis for an instruction set implementation in a computer system, the method including running a test-case in a first and a second model, determining if the test case failed in the first model and determining if the test case failed in the second model.

Abstract: A method and system for implementing store buffer allocation for variable length store data operations are provided. The method includes receiving a store address request and at least one store data request and stepping through data operations for each of the store data requests and an address range for the store data requests to determine alignment and data steering information used to select a storage buffer destination for the data in the store data requests. The method further includes determining availability of the storage buffer by maintaining a reservation list for each storage buffer, maintaining a count of the number of available entries for each storage buffer, updating the reservation list to reflect a reservation acceptance for designated available entries, and clearing entries upon completion of the processing of store data operations. The method also includes reserving the selected storage buffer when the number of available entries meets or exceeds the number of entries required for the data.

Abstract: A pipelined processor including an architecture for address generation interlocking, the processor including: an instruction grouping unit to detect a read-after-write dependency and to resolve instruction interdependency; an instruction dispatch unit (IDU) including address generation interlock (AGI) and operand fetching logic for dispatching an instruction to at least one of a load store unit and an execution unit; wherein the load store unit is configured with access to a data cache and to return fetched data to the execution unit; wherein the execution unit is configured to write data into a general purpose register bank; and wherein the architecture provides support for bypassing of results of a load multiple instruction for address generation while such instruction is executing in the execution unit before the general purpose register bank is written. A method and a computer system are also provided.

Abstract: A pipelined microprocessor configured for long operand instructions is disclosed. The microprocessor includes a memory unit and a load-store unit. The load store unit is coupled to the memory unit and includes a data formatter receiving information from the memory unit and including an operand selector and a shift register portion. The microprocessor also includes an execution unit coupled to the load-store unit and receiving operand information there from. The execution unit includes output latches coupled to a storage location within the execution unit for storing output information from the execution unit.

Abstract: Eliminating or reducing an operand line crossing penalty by performing an initial fetch for an operand from a data cache of a processor. The initial fetch is performed by allowing or permitting the initial fetch to occur unaligned with reference to a quadword boundary. A plurality of subsequent fetches for a corresponding plurality of operands from the data cache are performed wherein each of the plurality of subsequent fetches is aligned to any of a plurality of quadword boundaries to prevent each of a plurality of individual fetch requests from spanning a plurality of lines in the data cache. A steady stream of data is maintained by placing an operand buffer at an output of the data cache to store and merge data from the initial fetch and the plurality of subsequent fetches, and to return the stored and merged data to the processor.

Abstract: A method for processor error checking including receiving an instruction data, generating a pre-processing parity data based on the instruction data, maintaining the pre-processing parity data, processing the instruction data, generating a post-processing parity data based on the processed instruction data, checking for an error related to processing the instruction data by comparing the post-processing parity data to the pre-processing parity data, and transmitting an error signal that indicates the error related to processing the instruction data occurred if the post-processing parity data does not match the pre-processing parity data, wherein checking for the error related to processing the instruction data is performed without using a duplicate processing circuitry.

Abstract: A method and system for implementing store buffer allocation for variable length store data operations are provided. The method includes receiving a store address request and at least one store data request and stepping through data operations for each of the store data requests and an address range for the store data requests to determine alignment and data steering information used to select a storage buffer destination for the data in the store data requests. The method further includes determining availability of the storage buffer by maintaining a reservation list for each storage buffer, maintaining a count of the number of available entries for each storage buffer, updating the reservation list to reflect a reservation acceptance for designated available entries, and clearing entries upon completion of the processing of store data operations. The method also includes reserving the selected storage buffer when the number of available entries meets or exceeds the number of entries required for the data.

Abstract: System, method and computer program products for failure analysis implementing automated comparison of multiple reference models. An exemplary embodiment includes a method for failure analysis for an instruction set implementation in a computer system, the method including running a test-case in a first and a second model, determining if the test case failed in the first model and determining if the test case failed in the second model.