Patents by Inventor Vimal R. Patel

Vimal R. Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Electronic fuse cell and array
    Patent number: 9053889
    Abstract: Embodiments may include an eFuse cell. The eFuse cell may include an eFuse having a first end and a second end. A blowFET has a first source/drain area, a second source/drain area, and a first gate. The first source/drain area is coupled to the second end of the eFuse, the second source/drain area is coupled to ground, and the first gate is coupled to a first node. The eFuse cell includes a senseFET having a third source/drain area, a fourth source/drain area, and a second gate. The second gate is coupled to the first node, and the third source/drain area is coupled to a second node. The second node is coupled to an operation signal and the second end of the eFuse. The eFuse cell includes a select eFuse logic element having an input to receive a select eFuse signal and an output coupled to the first node.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: June 9, 2015
    Assignee: International Business Machines Corporation
    Inventors: Toshiaki Kirihata, Phil C. Paone, Vimal R. Patel, Gregory J. Uhlmann
  • ELECTRONIC FUSE CELL AND ARRAY
    Publication number: 20140253220
    Abstract: Embodiments may include an eFuse cell. The eFuse cell may include an eFuse having a first end and a second end. A blowFET has a first source/drain area, a second source/drain area, and a first gate. The first source/drain area is coupled to the second end of the eFuse, the second source/drain area is coupled to ground, and the first gate is coupled to a first node. The eFuse cell includes a senseFET having a third source/drain area, a fourth source/drain area, and a second gate. The second gate is coupled to the first node, and the third source/drain area is coupled to a second node. The second node is coupled to an operation signal and the second end of the eFuse. The eFuse cell includes a select eFuse logic element having an input to receive a select eFuse signal and an output coupled to the first node.
    Type: Application
    Filed: March 5, 2013
    Publication date: September 11, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toshiaki Kirihata, Phil C. Paone, Vimal R. Patel, Gregory J. Uhlmann
  • State sensing system for eFuse memory
    Patent number: 8780604
    Abstract: An eFuse circuit may include a wordline, a first eFuse, a first logic gate, a first blowFET, and a first bitline discharge device. The first eFuse may have a first end coupled to the wordline and a second end. The first eFuse may have a first resistance when unblown and a second resistance when blown. The first logic gate may be coupled to the first end of the first eFuse. The first logic gate may be capable of driving enough current to blow the first eFuse. The first blowFET may have a source coupled to a first supply voltage, a gate coupled to a program signal, and a drain coupled to the second end of the first eFuse. The first bitline discharge device may have a gate coupled to the second end of the first eFuse, a source coupled to the first supply voltage, and a drain coupled to a first bitline.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: July 15, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chihhung Liao, Phu Nguyen, Vimal R. Patel, George F. Paulik, Peder J. Paulson, Brian J. Reed, Salvatore N. Storino
  • STATE SENSING SYSTEM FOR EFUSE MEMORY
    Publication number: 20140003120
    Abstract: An eFuse circuit may include a wordline, a first eFuse, a first logic gate, a first blowFET, and a first bitline discharge device. The first eFuse may have a first end coupled to the wordline and a second end. The first eFuse may have a first resistance when unblown and a second resistance when blown. The first logic gate may be coupled to the first end of the first eFuse. The first logic gate may be capable of driving enough current to blow the first eFuse. The first blowFET may have a source coupled to a first supply voltage, a gate coupled to a program signal, and a drain coupled to the second end of the first eFuse. The first bitline discharge device may have a gate coupled to the second end of the first eFuse, a source coupled to the first supply voltage, and a drain coupled to a first bitline.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 2, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chihhung Liao, Phu Nguyen, Vimal R. Patel, George F. Paulik, Peder J. Paulson, Brian J. Reed, Salvatore N. Storino