Abstract: Disclosed is a wordline driver with an integrated voltage level shift function. This wordline driver receives a decoder output signal from a wordline address decoder operating at first voltage level. Based on the decoder output signal, it generates and outputs a wordline driving signal, which selectively activates or deactivates a selected wordline. To ensure that the selected wordline, when activated, is at a second voltage level that is higher than the first, the wordline driver uses a combination of clock signals received from multiple timing control blocks operating at the first voltage level and multiple logic gates operating the second voltage level. To ensure that this wordline driving signal remains low during power up when fluctuations occur due to the different voltage levels and, specifically, to ensure that the wordline driving signal only switches to high when it will be stable, the wordline driver can include a reset control block.

Abstract: Multiplexed latches include a multiplexor having a first data input, a second data input, a selection input, and a multiplexor output. A first latch has a first latch clock input, and a first latch output. A second latch has a second latch clock input, and a second latch output. The first latch output is connected to the first data input of the multiplexor, and the second latch output is connected to the second data input of the multiplexor. A feedback loop connects the multiplexor output to the first latch clock input and the second latch clock input. When the selection signal is received by the multiplexor, the feedback loop feeds the output from the multiplexor back to the latches to maintain the existing latch output until the clock signal transitions, to avoid glitches in the multiplexor output when the selection signal and clock signal are not synchronized.