Patents by Inventor Vinay G. Rao

Vinay G. Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12131022
    Abstract: An apparatus in one embodiment includes at least one processing device comprising a processor coupled to a memory. The at least one processing device is configured to obtain in a host device asymmetric access state information for one or more logical storage devices each accessible in at least first and second storage systems, and to determine, based at least in part on the asymmetric access state information obtained for the one or more logical storage devices, local-remote designations of respective ones of the first and second storage systems. The asymmetric access state information for a given one of the logical storage devices illustratively comprises, for each of two or more storage controllers of each of the first and second storage systems, information indicating whether a corresponding set of paths is in an active-optimized (AO) state or an active-non-optimized (ANO) state.
    Type: Grant
    Filed: January 12, 2023
    Date of Patent: October 29, 2024
    Assignee: Dell Products L.P.
    Inventors: Rimpesh Patel, Amit Pundalik Anchi, Vinay G. Rao
  • Publication number: 20240329277
    Abstract: Embodiments are disclosed for crash detection on one or more mobile devices (e.g., smartwatch and/or smartphone. In some embodiments, a method comprises: detecting a crash event on a crash device; extracting multimodal features from sensor data generated by multiple sensing modalities of the crash device; computing a plurality of crash decisions based on a plurality of machine learning models applied to the multimodal features, wherein at least one multimodal feature is a rotation rate about a mean axis of rotation; and determining that a severe vehicle crash has occurred involving the crash device based on the plurality of crash decisions and a severity model.
    Type: Application
    Filed: June 7, 2024
    Publication date: October 3, 2024
    Inventors: Vinay R. Majjigi, Bharath Narasimha Rao, Sriram Venkateswaran, Aniket Aranake, Tejal Bhamre, Alexandru Popovici, Parisa Dehleh Hossein Zadeh, Yann Jerome Julien Renard, Yi Wen Liao, Stephen P. Jackson, Rebecca L. Clarkson, Henry Choi, Paul D. Bryan, Mrinal Agarwal, Ethan Goolish, Richard G. Liu, Omar Aziz, Alvaro J. Melendez Hasbun, David Ojeda Avellaneda, Sunny Kai Pang Chow, Pedro O. Varangot, Tianye Sun, Karthik Jayaraman Raghuram, Hung A. Pham
  • Patent number: 12105956
    Abstract: At least one processing device is configured to control delivery of input-output (IO) operations from a host device to a storage system over selected ones of a plurality of paths through a network. The at least one processing device is further configured to designate one or more of the paths as being associated with a link performance issue, to temporarily suspend utilization of the one or more designated paths for delivery of IO operations from the host device to the storage system, to detect a configuration change that is indicative of potential resolution of the link performance issue, and to resume utilization of the one or more designated paths responsive to the detected configuration change. The at least one processing device illustratively comprises a multi-path input-output (MPIO) driver of the host device.
    Type: Grant
    Filed: September 23, 2022
    Date of Patent: October 1, 2024
    Assignee: Dell Products L.P.
    Inventors: Sanjib Mallick, Vinay G. Rao, Anthony D. Fong, Scott Rowlands, Arieh Don
  • Publication number: 20240311025
    Abstract: An apparatus illustratively comprises at least one processing device that comprises a processor coupled to a memory. The at least one processing device is configured to maintain in a host device queue depth measures for respective paths over which input-output operations are delivered from the host device to a storage system, and to control path selection for delivery of additional input-output operations from the host device to the storage system based at least in part on the queue depth measures maintained for the paths. The at least one processing device may comprise at least one multi-path input-output driver of the host device, with maintaining the queue depth measures and controlling the path selection being performed at least in part by the at least one multi-path input-output driver of the host device. The multi-path input-output driver illustratively comprises a lockless polled-mode driver implemented in a user space of the host device.
    Type: Application
    Filed: March 14, 2023
    Publication date: September 19, 2024
    Inventors: Vinay G. Rao, Mohammad Salim Akhtar, Madhu Tarikere
  • Publication number: 20240272795
    Abstract: Techniques for dynamically configuring a multi-site storage system such as a metro cluster using input/output (IO) response time (RT) hints from a host computer. The techniques include receiving IO RT hints at each storage appliance of the multi-site storage system from the host computer, which is initially identified as “local” or “remote” relative to a physical location of the storage appliance. The techniques further include modifying, by the storage appliance, an initial local or remote identification of the host computer relative to the physical location of the storage appliance based on the received IO RT hints, dynamically changing, by the storage appliance, states of IO paths between the host computer and nodes of the storage appliance based on the modified local or remote identification of the host computer, and providing, by the storage appliance, notification of the changed states of the IO paths to the host computer.
    Type: Application
    Filed: February 13, 2023
    Publication date: August 15, 2024
    Inventors: Vinay G. Rao, Vasudevan Subramanian, Sanjib Mallick
  • Publication number: 20240256125
    Abstract: An apparatus in one embodiment includes at least one processing device comprising a processor coupled to a memory. The at least one processing device is configured to identify a logical storage device accessible in at least first and second storage systems, to measure response times for accessing the logical storage device in each of the first and second storage systems, and to modify, based at least in part on the measured response times, asymmetric access state settings for the logical storage device. Modifying asymmetric access state settings for the logical storage device in some embodiments illustratively comprises modifying asymmetric logical unit access (ALUA) or asymmetric namespace access (ANA) state settings for the logical storage device. Such modifications are illustratively performed in a dynamic manner that responds to variations in the measured response times so as to facilitate load balancing across storage controllers of the first and second storage systems.
    Type: Application
    Filed: January 30, 2023
    Publication date: August 1, 2024
    Inventors: Vinay G. Rao, Vasudevan Subramanian, Sanjib Mallick
  • Publication number: 20240248634
    Abstract: An apparatus in one embodiment includes at least one processing device comprising a processor coupled to a memory. The at least one processing device is configured to obtain, in a host device, inter-system response time information based at least in part on one or more response times measured by at least one of first and second storage systems relative to another one of the first and second storage systems, and to automatically control, based at least in part on the obtained inter-system response time information, active-standby designations for respective ones of the first and second storage systems. For example, in some embodiments, automatically controlling active-standby designations for respective ones of the first and second storage systems illustratively comprises controlling activation of an active-standby mode of operation based at least in part on comparison of at least a portion of the inter-system response time information to one or more specified thresholds.
    Type: Application
    Filed: January 24, 2023
    Publication date: July 25, 2024
    Inventors: Vinay G. Rao, Sanjib Mallick, Benjamin Yoder, Arieh Don
  • Publication number: 20240241638
    Abstract: An apparatus in one embodiment includes at least one processing device comprising a processor coupled to a memory. The at least one processing device is configured to obtain in a host device asymmetric access state information for one or more logical storage devices each accessible in at least first and second storage systems, and to determine, based at least in part on the asymmetric access state information obtained for the one or more logical storage devices, local-remote designations of respective ones of the first and second storage systems. The asymmetric access state information for a given one of the logical storage devices illustratively comprises, for each of two or more storage controllers of each of the first and second storage systems, information indicating whether a corresponding set of paths is in an active-optimized (AO) state or an active-non-optimized (ANO) state.
    Type: Application
    Filed: January 12, 2023
    Publication date: July 18, 2024
    Inventors: Rimpesh Patel, Amit Pundalik Anchi, Vinay G. Rao
  • Patent number: 12032842
    Abstract: An apparatus in one embodiment includes at least one processing device comprising a processor coupled to a memory. The at least one processing device is configured to obtain in a host device information characterizing local-remote designations of respective first and second storage systems, one of which is designated as local and one of which is designated as remote, and to adjust path selection in a multi-path layer of the host device based at least in part on the obtained information characterizing the local-remote designations of the respective first and second storage systems. In some embodiments, a given logical storage device is accessible to the multi-path layer of the host device via a first set of paths to the first storage system and a second set of paths to the second storage system, and adjusting path selection in the multi-path layer comprises adjusting weights assigned to respective ones of the paths.
    Type: Grant
    Filed: October 10, 2022
    Date of Patent: July 9, 2024
    Assignee: Dell Products L.P.
    Inventors: Rimpesh Patel, Amit Pundalik Anchi, Vinay G. Rao
  • Patent number: 12001679
    Abstract: An apparatus comprises a processing device configured to detect an input-output (IO) pressure condition relating to at least one logical storage volume of a storage system, to receive IO operations directed to the at least one logical storage volume, to extract processing entity identifiers from respective ones of the received IO operations, and to perform IO throttling for the at least one logical storage volume based at least in part on the extracted processing entity identifiers. For example, a first group of one or more of the IO operations each having a first processing entity identifier may be subject to the IO throttling, while a second group of one or more of the IO operations each having a second processing entity identifier different than the first processing entity identifier is not subject to the IO throttling. Other differences in IO throttling can be implemented using the extracted processing entity identifiers.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: June 4, 2024
    Assignee: Dell Products L.P.
    Inventors: Sanjib Mallick, Vinay G. Rao, Arieh Don
  • Patent number: 12001714
    Abstract: An apparatus in one embodiment comprises at least one processing device that includes a processor coupled to a memory. The processing device is configured to obtain buffer availability information from a storage system, the buffer availability information indicating that the storage system is currently experiencing a deficiency in a number of available buffers of a given one of at least first and second different buffer sizes supported by the storage system, and to select particular input-output operations for delivery to the storage system over one or more networks based at least in part on the obtained buffer availability information. Obtaining the buffer availability information from the storage system illustratively comprises sending at least one command from a host device to the storage system. First and second different buffer types having the first and second different buffer sizes may comprise respective different write buffer types within a larger write buffer.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: June 4, 2024
    Assignee: Dell Products L.P.
    Inventors: Sanjib Mallick, Vinay G. Rao, Krishna Deepak Nuthakki, Arieh Don
  • Publication number: 20240118820
    Abstract: An apparatus in one embodiment includes at least one processing device comprising a processor coupled to a memory. The at least one processing device is configured to obtain in a host device information characterizing local-remote designations of respective first and second storage systems, one of which is designated as local and one of which is designated as remote, and to adjust path selection in a multi-path layer of the host device based at least in part on the obtained information characterizing the local-remote designations of the respective first and second storage systems. In some embodiments, a given logical storage device is accessible to the multi-path layer of the host device via a first set of paths to the first storage system and a second set of paths to the second storage system, and adjusting path selection in the multi-path layer comprises adjusting weights assigned to respective ones of the paths.
    Type: Application
    Filed: October 10, 2022
    Publication date: April 11, 2024
    Inventors: Rimpesh Patel, Amit Pundalik Anchi, Vinay G. Rao
  • Patent number: 11954344
    Abstract: An apparatus comprises at least one processing device. The at least one processing device is configured, for each of a plurality of logical storage devices of a storage system, to determine in a multi-path layer of a layered software stack of a host device a performance level for that logical storage device, to communicate the performance levels for respective ones of the logical storage devices from the multi-path layer of the layered software stack of the host device to at least one additional layer of the software stack above the multi-path layer, and to select particular ones of the logical storage devices for assignment to particular storage roles in the additional layer based at least in part on the communicated performance levels. The additional layer in some embodiments comprises an application layer configured to automatically select a particular one of the logical storage devices for a particular storage role.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: April 9, 2024
    Assignee: EMC IP Holding Company LLC
    Inventors: Sanjib Mallick, Vinay G. Rao, Jay Jung, Arieh Don
  • Publication number: 20240103724
    Abstract: At least one processing device is configured to control delivery of input-output (TO) operations from a host device to a storage system over selected ones of a plurality of paths through a network. The at least one processing device is further configured to designate one or more of the paths as being associated with a link performance issue, to temporarily suspend utilization of the one or more designated paths for delivery of IO operations from the host device to the storage system, to detect a configuration change that is indicative of potential resolution of the link performance issue, and to resume utilization of the one or more designated paths responsive to the detected configuration change. The at least one processing device illustratively comprises a multi-path input-output (MPIO) driver of the host device.
    Type: Application
    Filed: September 23, 2022
    Publication date: March 28, 2024
    Inventors: Sanjib Mallick, Vinay G. Rao, Anthony D. Fong, Scott Rowlands, Arieh Don
  • Publication number: 20240103729
    Abstract: A processing device illustratively includes a processor coupled to a memory, and is configured to initiate a background copy process in a host device to copy data from a first storage system to a second storage system. The processing device receives input-output (IO) processing pressure feedback from at least one of the first and second storage systems, and adjusts one or more characteristics of the background copy process based at least in part on the received IO processing pressure feedback. The processing device may comprise, for example, host level mirroring (HLM) logic configured to control execution of the background copy process for one or more logical storage devices. Adjusting one or more characteristics of the background copy process based at least in part on the received IO processing pressure feedback may comprise, for example, reducing a rate of the background copy process responsive to the received IO processing pressure feedback.
    Type: Application
    Filed: September 28, 2022
    Publication date: March 28, 2024
    Inventors: Sanjib Mallick, Vinay G. Rao, Arieh Don
  • Patent number: 11934659
    Abstract: A processing device illustratively includes a processor coupled to a memory, and is configured to initiate a background copy process in a host device to copy data from a first storage system to a second storage system. The processing device receives input-output (IO) processing pressure feedback from at least one of the first and second storage systems, and adjusts one or more characteristics of the background copy process based at least in part on the received IO processing pressure feedback. The processing device may comprise, for example, host level mirroring (HLM) logic configured to control execution of the background copy process for one or more logical storage devices. Adjusting one or more characteristics of the background copy process based at least in part on the received IO processing pressure feedback may comprise, for example, reducing a rate of the background copy process responsive to the received IO processing pressure feedback.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: March 19, 2024
    Assignee: Dell Products L.P.
    Inventors: Sanjib Mallick, Vinay G. Rao, Arieh Don
  • Patent number: 11934679
    Abstract: A method, computer program product, and computing system for dividing a volume into a plurality of segments. The plurality of segments may be assigned to a plurality of nodes of a multi-node storage system. One or more input/output (IO) request paths for accessing the plurality of segments may be defined based upon, at least in part, assigning the plurality of segments to the plurality of nodes.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: March 19, 2024
    Assignee: EMC IP Holding Company, LLC
    Inventors: David Meiri, Vinay G. Rao, Sanjib Mallick
  • Patent number: 11928365
    Abstract: An apparatus comprises at least one processing device comprising a processor coupled to a memory. The at least one processing device is configured to receive in a storage system, from a host device, mapping information associating a key identifier of a datastore-level key with a corresponding datastore comprising multiple logical storage devices of the storage system, to store the mapping information in a datastore-level key data structure of the storage system, to utilize the key identifier to obtain in the storage system the datastore-level key from a key management server external to the storage system, and responsive to receipt of at least one IO operation from the host device relating to at least one of reading or writing encrypted data of at least one of the logical storage devices of the datastore, to utilize the obtained datastore-level key to access the encrypted data in unencrypted form in the storage system.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: March 12, 2024
    Assignee: EMC IP Holding Company LLC
    Inventors: Amit Pundalik Anchi, Vinay G. Rao, Srinivas Kangyampeta, Madhu Tarikere
  • Publication number: 20240061609
    Abstract: An apparatus in one embodiment comprises at least one processing device that includes a processor coupled to a memory. The processing device is configured to obtain buffer availability information from a storage system, the buffer availability information indicating that the storage system is currently experiencing a deficiency in a number of available buffers of a given one of at least first and second different buffer sizes supported by the storage system, and to select particular input-output operations for delivery to the storage system over one or more networks based at least in part on the obtained buffer availability information. Obtaining the buffer availability information from the storage system illustratively comprises sending at least one command from a host device to the storage system. First and second different buffer types having the first and second different buffer sizes may comprise respective different write buffer types within a larger write buffer.
    Type: Application
    Filed: August 16, 2022
    Publication date: February 22, 2024
    Inventors: Sanjib Mallick, Vinay G. Rao, Krishna Deepak Nuthakki, Arieh Don
  • Patent number: 11886711
    Abstract: An apparatus comprises at least one processing device. The at least one processing device is configured to identify at least one logical storage device that has a first service level objective and is exhibiting a deficiency in one or more performance metrics, to identify one or more additional logical storage devices each having a second service level objective lower than the first service level objective and not exhibiting a deficiency in the one or more performance metrics, to generate at least one false-positive signal specifying the one or more additional logical storage devices as each exhibiting a deficiency in the one or more performance metrics, and to provide the at least one false-positive signal to at least one host device. The at least one host device is configured to respond to the at least one false-positive signal by throttling input-output operations for the one or more additional logical storage devices.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: January 30, 2024
    Assignee: Dell Products L.P.
    Inventors: Sanjib Mallick, Vinay G. Rao, Jaeyoo Jung, Arieh Don