Patents by Inventor Vinay Hanumaiah

Vinay Hanumaiah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11699093
    Abstract: Techniques for generating and executing an execution plan for a machine learning (ML) model using one of an edge device and a non-edge device are described. In some examples, a request for the generation of the execution plan includes at least one objective for the execution of the ML model and the execution plan is generated based at least in part on comparative execution information and network latency information.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: July 11, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Nagajyothi Nookula, Poorna Chand Srinivas Perumalla, Aashish Jindia, Danjuan Ye, Eduardo Manuel Calleja, Song Ge, Vinay Hanumaiah, Wanqiang Chen, Safeer Mohiuddin, Romi Boimer, Madan Mohan Rao Jampani, Fei Chen
  • Patent number: 11544577
    Abstract: Techniques for utilizing adaptable filters for edge-based deep learning models are described. Filters may be utilized by an edge electronic device to filter elements of an input data stream so that only a subset of the elements are used as inputs to a machine learning model run by the electronic device, enabling successful operation despite the input data stream potentially being generated at a higher rate than a rate in which the ML model can be executed. The filter can be a differential-type filter that generates difference representations between consecutive elements of the data stream to determine which elements are to be passed on for the ML model, a “smart” filter such as a neural network trained using outputs from the ML model allowing the filter to “learn” which elements are the most likely to be of value to be passed on, or a combination of both.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: January 3, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Nagajyothi Nookula, Poorna Chand Srinivas Perumalla, Aashish Jindia, Eduardo Manuel Calleja, Vinay Hanumaiah
  • Patent number: 10810471
    Abstract: Techniques for intelligent coalescing of media streams are described. A coalesce engine receives multiple media streams, such as audio or video streams, that are misaligned. The coalesce engine can analyze the media streams by comparing representations of elements of the media streams to detect the misalignment. The coalesce engine may determine an offset amount representing the misalignment, and if the offset amount meets or exceeds a threshold the coalesce engine can work to eliminate the misalignment by introducing one or more artificial delays before sending elements of ones of the media streams that are “ahead” of others of the streams. The coalese engine can additionally or alternatively send feedback to sources of the media streams, causing the source(s) to attempt to mitigate the misalignment.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: October 20, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Poorna Chand Srinivas Perumalla, Nagajyothi Nookula, Eduardo Manuel Calleja, Aashish Jindia, Vinay Hanumaiah
  • Publication number: 20190220783
    Abstract: Techniques for generating and executing an execution plan for a machine learning (ML) model using one of an edge device and a non-edge device are described. In some examples, a request for the generation of the execution plan includes at least one objective for the execution of the ML model and the execution plan is generated based at least in part on comparative execution information and network latency information.
    Type: Application
    Filed: January 16, 2018
    Publication date: July 18, 2019
    Inventors: Nagajyothi NOOKULA, Poorna Chand Srinivas PERUMALLA, Aashish JINDIA, Danjuan YE, Eduardo Manuel CALLEJA, Song GE, Vinay HANUMAIAH, Wanqiang CHEN, Safeer MOHIUDDIN, Romi BOIMER, Madan Mohan Rao JAMPANI, Fei CHEN
  • Patent number: 10133323
    Abstract: A control system for use with a processor includes: (i) a controller configured to receive prediction information for a predicted temperature associated with the processor, and to determine a speed of operation for the processor based at least on a thermal model of the processor and the predicted temperature, where the speed supports an operational objective of the processor; and (ii) an error estimator that is separate from the controller, and that is configured to receive temperature information obtained from the processor operating at the speed, to determine updated prediction information based, at least in part, on the temperature information, and to output the updated prediction information to the controller.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: November 20, 2018
    Assignee: Arizona Board of Regents for and on behalf of Arizona State University
    Inventors: Vinay Hanumaiah, Sarma Vrudhula, Benjamin Gaudette
  • Patent number: 9933825
    Abstract: An example process for controlling a processor may include: (i) obtaining parameters associated with operation of a processor, where each of the parameters has a different time scale; (ii) performing an iterative process to identify ones of the parameters that achieve a particular energy efficiency in the processor, where the energy efficiency of the processor corresponds to a quasi-concave function having a maximum that corresponds to the ones of the parameters; and (iii) controlling the processor using the ones of the parameters.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: April 3, 2018
    Assignee: Arizona Board of Regents for and on behalf of Arizona State University
    Inventors: Vinay Hanumaiah, Sarma Vrudhula
  • Publication number: 20140277815
    Abstract: A control system for use with a processor includes: (i) a controller configured to receive prediction information for a predicted temperature associated with the processor, and to determine a speed of operation for the processor based at least on a thermal model of the processor and the predicted temperature, where the speed supports an operational objective of the processor; and (ii) an error estimator that is separate from the controller, and that is configured to receive temperature information obtained from the processor operating at the speed, to determine updated prediction information based, at least in part, on the temperature information, and to output the updated prediction information to the controller.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 18, 2014
    Applicant: Arizona Board of Regents for and on behalf of Arizona State University
    Inventors: Vinay Hanumaiah, Sarma Vrudhula, Benjamin Gaudette
  • Publication number: 20140281609
    Abstract: An example process for controlling a processor may include: (i) obtaining parameters associated with operation of a processor, where each of the parameters has a different time scale; (ii) performing an iterative process to identify ones of the parameters that achieve a particular energy efficiency in the processor, where the energy efficiency of the processor corresponds to a quasi-concave function having a maximum that corresponds to the ones of the parameters; and (iii) controlling the processor using the ones of the parameters.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 18, 2014
    Applicant: Arizona Board of Regents for and on behalf of Arizona State University
    Inventors: Vinay Hanumaiah, Sarma Vrudhula