Patents by Inventor Vinay Iyengar

Vinay Iyengar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230419711
    Abstract: Systems and methods for extracting data from electronic documents using optical character recognition (OCR) and non-OCR based text extraction. A server computing device initiates non-OCR based text extraction for each page of an electronic document. The server calculates a document text coverage percentage corresponding to the non-OCR based text extraction for the whole document and, in response to determining that the document text coverage percentage is below a first threshold, initiates OCR for the document. The server calculates a page text coverage percentage corresponding to the non-OCR based text extraction for one or more pages of the electronic document and, in response to determining that the page text coverage percentage is below a second threshold, initiates OCR for the pages. The server combines first text extracted from the electronic document using non-OCR based text extraction and second text extracted from the electronic document using OCR.
    Type: Application
    Filed: June 27, 2022
    Publication date: December 28, 2023
    Inventors: Keerthan Ramnath, Punitha Chandrasekar, Hui Su, Shyam Subramanian, Rachna Saxena, Mohamed Mahdi Alouane, Vinay Iyengar
  • Patent number: 11657078
    Abstract: Methods and apparatuses are described for automatically identifying text sections of a document to generate a searchable hierarchical data structure. A computing device receives a document comprising text entities and converts the document from a first format to a second format, including generating metadata associated with text alignment, text position, text spacing, or fonts. The computing device extracts the text blocks, including determining coordinates associated with each text block using the metadata. The computing device determines document sections using the document metadata by identifying strings in the extracted text blocks that indicate a presence of a bullet point in the document, assigns a hierarchical category to each identified document section, and inserts text of each document section into a hierarchical data structure based upon the assigned hierarchical category.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: May 23, 2023
    Assignee: FMR LLC
    Inventors: Ananya Bal, Punitha Chandrasekar, Vinay Iyengar, Bidhan Roy
  • Publication number: 20230119590
    Abstract: Methods and apparatuses are described for automatically identifying text sections of a document to generate a searchable hierarchical data structure. A computing device receives a document comprising text entities and converts the document from a first format to a second format, including generating metadata associated with text alignment, text position, text spacing, or fonts. The computing device extracts the text blocks, including determining coordinates associated with each text block using the metadata. The computing device determines document sections using the document metadata by identifying strings in the extracted text blocks that indicate a presence of a bullet point in the document, assigns a hierarchical category to each identified document section, and inserts text of each document section into a hierarchical data structure based upon the assigned hierarchical category.
    Type: Application
    Filed: October 14, 2021
    Publication date: April 20, 2023
    Inventors: Ananya Bal, Punitha Chandrasekar, Vinay Iyengar, Bidhan Roy
  • Patent number: 9520194
    Abstract: A pre-computation based TCAM configured to reduce the number of match lines being pre-charged during a search operation to save power is disclosed. The pre-computation based TCAM stores additional information in a secondary TCAM that can be used to determine which match lines in a primary TCAM storing data words to be searched need not be pre-charged because they are associated with data words guaranteed to not match. The additional information stored in secondary TCAM can include a pre-computation word that represents a range inclusive of a lower and upper bound of a number of ones or zeroes possible in a corresponding data word stored in the primary TCAM.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: December 13, 2016
    Assignee: Broadcom Corporation
    Inventor: Vinay Iyengar
  • Publication number: 20150235701
    Abstract: A pre-computation based TCAM configured to reduce the number of match lines being pre-charged during a search operation to save power is disclosed. The pre-computation based TCAM stores additional information in a secondary TCAM that can be used to determine which match lines in a primary TCAM storing data words to be searched need not be pre-charged because they are associated with data words guaranteed to riot match. The additional information stored in secondary TCAM can include a pre-computation word that represents a range inclusive of a lower and upper bound of a number of ones or zeroes possible in a corresponding data word stored in the primary TCAM.
    Type: Application
    Filed: April 30, 2015
    Publication date: August 20, 2015
    Applicant: Broadcom Corporation
    Inventor: Vinay IYENGAR
  • Patent number: 9070435
    Abstract: A pre-computation based TCAM configured to reduce the number of match lines being pre-charged during a search operation to save power is disclosed. The pre-computation based TCAM stores additional information in a secondary TCAM that can be used to determine which match lines in a primary TCAM storing data words to be searched need not be pre-charged because they are associated with data words guaranteed to not match. The additional information stored in secondary TCAM can include a pre-computation word that represents a range inclusive of a lower and upper bound of a number of ones or zeroes possible in a corresponding data word stored in the primary TCAM.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: June 30, 2015
    Assignee: Broadcom Corporation
    Inventor: Vinay Iyengar
  • Patent number: 8787059
    Abstract: A content addressable memory (CAM) device has an array including a plurality of CAM rows that are partitioned into row segments, wherein a respective row includes a first row segment including a number of first CAM cells coupled to a first match line segment, a second row segment including a number of second CAM cells coupled to a second match line segment, and a circuit to selectively pre-charge the first match line segment in response to a value indicating whether data stored in the first row segment of the respective row is the same as data stored in the first row segment of another row. Power consumption can be reduced during compare operations in which the first row segment of another row that stores the same data as the first row segment of the respective row is not enabled.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: July 22, 2014
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Vinay Iyengar
  • Patent number: 8730704
    Abstract: A CAM device is disclosed that includes an array of CAM cells in which the compare circuits of groups of CAM cells are connected together using a conductive layer interposed between a polysilicon layer of the CAM device and the metal-1 layer of the CAM device. This allows the data lines (e.g., the bit lines and/or comparand lines) of the CAM array to be formed in the metal-1 layer of the CAM device, which in turn allows the match lines of the CAM array to be formed in the metal-2 layer of the CAM device. The conductive layer, which may be a silicide layer, is connected to the match line by a via extending from the conductive layer through the metal-1 layer to the metal-2 layer.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: May 20, 2014
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Bindiganavale S. Nataraj, John Zimmer, Sandeep Khanna, Vinay Iyengar, Chetan Deshpande
  • Publication number: 20140085958
    Abstract: A pre-computation based TCAM configured to reduce the number of match lines being pre-charged during a search operation to save power is disclosed. The pre-computation based TCAM stores additional information in a secondary TCAM that can be used to determine which match lines in a primary TCAM storing data words to be searched need not be pre-charged because they are associated with data words guaranteed to not match. The additional information stored in secondary TCAM can include a pre-computation word that represents a range inclusive of a lower and upper bound of a number of ones or zeroes possible in a corresponding data word stored in the primary TCAM.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Applicant: Broadcom Corporation
    Inventor: Vinay IYENGAR
  • Patent number: 8031501
    Abstract: Present embodiments describe a CAM device having a segmented CAM array. Each segment of the CAM array, or cell blocks, includes one or more rows of CAM cells. One or more of the cell blocks in the CAM array are selectively enabled during a search operation based on a detected matching condition of another cell block. By selectively enabling cell blocks during search operations only when needed, energy consumption is reduced. Selectively enabling a cell block includes selectively pre-charging match lines to the cell block, selectively enabling word lines to the cell block, and selectively enabling comparand line to the cell block. In accordance with certain embodiments, the CAM device is configurable to perform search operations in a pipelined manner. Accordingly, the CAM device is capable of performing multiple search operations simultaneously.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: October 4, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Bindiganavale S. Nataraj, Chetan Deshpande, Vinay Iyengar, Sandeep Khanna
  • Patent number: 7920399
    Abstract: A content addressable memory (CAM) device includes a CAM array and a configuration circuit. The CAM array has a plurality of rows of CAM cells, each row segmented into a plurality of row segments, each row segment including a plurality of CAM cells coupled to a corresponding match line segment, and a match line control circuit having an input coupled to the corresponding match line segment, an output coupled to the match line segment in a next row segment, and a control terminal to receive a corresponding enable signal. The configuration circuit has an input to receive configuration information indicative of a width and depth configuration of the CAM array and having outputs to generate the enable signals.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: April 5, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Bindiganavale S. Nataraj, Vinay Iyengar, Chetan Deshpande, Sandeep Khanna
  • Patent number: 7920398
    Abstract: A content addressable memory (CAM) device having any number of rows, each of the rows including a match line connected to a plurality of CAM cells, a match line detector circuit, and a pre-charge circuit. The detector circuit detects a voltage of the match line and generates a feedback signal based on the detected match line voltage. The pre-charge circuit adaptively charges the match line in response to the feedback signal.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: April 5, 2011
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Sandeep Khanna, Bindiganavale S. Nataraj, Chetan Deshpande, Vinay Iyengar
  • Patent number: 7848129
    Abstract: A content addressable memory (CAM) device includes a comparand register, a CAM array, and partition logic. The comparand register has inputs to receive a search key, and outputs coupled to the CAM array, which includes a plurality of individually selectable sub-arrays. Each sub-array includes a number of rows of CAM cells and a control circuit, wherein each row of CAM cells is coupled to a match line, and wherein the control circuit has an input to receive a corresponding sub-array enable signal. The partition logic has an input to receive a partition select signal, and is configured to generate the sub-array enable signals in response to the partition select signal. The control circuits selectively propagate the search key through the sub-arrays in response to the sub-array enable signals.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: December 7, 2010
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Chetan Deshpande, Vinay Iyengar, Bindiganavale S. Nataraj
  • Patent number: 7461295
    Abstract: A method of testing a semiconductor device having a pipelined architecture. Operation of a first pipeline stage of the semiconductor is disabled during a first pipelined operation to establish test data at an input of a second pipeline stage of the semiconductor device. A second pipelined operation is executed to enable the second pipeline stage to generate an intermediate result using the test data. A final result of the second pipelined operation is evaluated to determine whether the second pipeline stage produced a correct intermediate result.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: December 2, 2008
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Vinay Iyengar, Bindiganavale S. Nataraj