Abstract: A method is provided for cleaning a semiconductor topography having one or more contact openings etched through a dielectric layer formed on a substrate. The method substantially eliminates unfilled contacts and reduces contact defects. Generally, the method involves: (i) heating the substrate in a processing chamber to a predetermined temperature; (ii) generating a plasma upstream of the process chamber using a microwave generator and a process gas comprising nitrogen and hydrogen or argon and helium; and (iii) introducing the plasma into the process chamber to clean the semiconductor topography. As the clean is accomplished substantially without the use of an organic solvent, galvanic corrosion of contacts subsequently formed in the contact openings is substantially eliminated. Other embodiments are also described.

Abstract: A method is provided for forming a borderless contact to a local interconnect (LI) line on a substrate. Generally, the method includes steps of (i) depositing a nitride layer over a number of LI lines on the substrate, to substantially cover the LI lines; (ii) etching the nitride layer to form spacers adjacent to sidewalls of at least one of the number of LI lines and to expose at least a portion of a top surface of the LI line; (iii) depositing an inter-layer dielectric, such as an oxide, over the number of LI lines on the substrate and the spacers formed adjacent thereto; and (iv) performing a contact etch to etch contact openings through the inter-layer dielectric to expose the portion of the top surface of the underlying LI line. Other embodiments are also disclosed.

Abstract: A method of removing a defect from a gate stack on a substrate, comprises treating the gate stack with a plasma. The plasma comprises fluorine, the gate stack comprises a gate layer and a metallic layer, and substantially no photoresist is present on the substrate.

Abstract: A method for processing a semiconductor topography which includes removing metal oxide layers from the bottom of contact openings is provided. In some embodiments, the method may include etching openings within a dielectric layer to expose conductive and silicon surfaces within the semiconductor topography is provided. In such cases, the method further includes exposing the semiconductor topography to an etch process adapted to remove metal oxide material from the conductive surfaces without substantially removing material from the silicon surfaces. In some cases, the etch chemistry used for the etch process may include sulfuric acid. In addition or alternatively, the etch chemistry may include hydrogen peroxide. In any case, the etch chemistry may be distinct from chemistries used to remove residual matter generated from the etch process used to form the openings within the dielectric and/or the removal of the masking layer used to pattern the openings.