Patents by Inventor Vinay Nair
Vinay Nair has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11954099Abstract: Systems and methods for implementing a multi-factor financial ontology framework are disclosed. In exemplary embodiments, a computer-implement method executing on a computer receives a natural language query from a user device and parses the query to determine a set of natural language terms associated with financial product criteria. The computer system maps the natural language terms to data nodes that implement the financial ontology framework and identifies responsive financial products from those data nodes. The computer system transmits the data corresponding to the responsive financial product to the user device.Type: GrantFiled: November 5, 2021Date of Patent: April 9, 2024Assignee: Magnifi LLCInventors: Vinay Nair, Aniket Vijaykumar Jain
-
Patent number: 11915777Abstract: Some embodiments include an integrated assembly having first and second source/drain regions laterally offset from one another. Metal silicide is adjacent to lateral surfaces of the source/drain regions. Metal is adjacent to the metal silicide. Container-shaped first and second capacitor electrodes are coupled to the source/drain regions through the metal silicide and the metal. Capacitor dielectric material lines interior surfaces of the container-shaped first and second capacitor electrodes, A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends into the lined first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: February 10, 2022Date of Patent: February 27, 2024Assignee: Micron Technology, Inc.Inventors: Che-Chi Lee, Terrence B. McDaniel, Kehao Zhang, Albert P. Chan, Clement Jacob, Luca Fumagalli, Vinay Nair
-
Publication number: 20240064972Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes data lines; first structures located in a first region, electrically separated from each other, and including first conductive contacts coupled to the data lines; second conductive contacts located in the first region and coupled to memory elements of the apparatus; second structures located in a second region, electrically separated from each other, and including respective gates of transistors in the second region; a first dielectric material formed in the second region and including a first portion and a second portion, the first portion formed at a first side of a structure among the second structures, the second portion formed at a second side first of the structure; and a second dielectric material formed over the first structures and the second structure. A portion of the second dielectric material contacts the first portion of the first dielectric material.Type: ApplicationFiled: August 22, 2022Publication date: February 22, 2024Inventors: Si-Woo Lee, Terrence B. Mcdaniel, Guangjun Yang, Vinay Nair
-
Publication number: 20240038588Abstract: A method of forming a microelectronic device comprises forming interlayer dielectric material over a base structure comprising semiconductive structures separated from one another by insulative structures. Sacrificial line structures separated from one another by trenches are formed over the interlayer dielectric material. The sacrificial line structures horizontally overlap some of the semiconductive structures, and the trenches horizontally overlap some other of the semiconductive structures. Plug structures are formed within horizontal areas of the trenches and extend through the interlayer dielectric material and into the some other of the semiconductive structures. The sacrificial line structures are replaced with additional trenches. Conductive contact structures are formed within horizontal areas of the additional trenches and extend through the interlayer dielectric material and into the some of the semiconductive structures.Type: ApplicationFiled: July 27, 2022Publication date: February 1, 2024Inventors: Terrence B. McDaniel, Vinay Nair, Russell A. Benson, Christopher W. Petz, Si-Woo Lee, Silvia Borsari, Ping Chieh Chiang, Luca Fumagalli
-
Publication number: 20230343815Abstract: Methods, apparatuses, and systems related to depositing a storage node material are described. An example method includes forming a semiconductor structure including a support structure having a first silicate material over a bottom nitride material, a first nitride material over the first silicate material, a second silicate material over the first nitride material, and a second nitride material over the second silicate material. The method further includes removing portions of the second nitride material. The method further includes depositing a third silicate material over the second nitride material and a portion of the second silicate material. The method further includes forming an opening through the semiconductor structure. The method further includes depositing a storage node material within the opening.Type: ApplicationFiled: April 22, 2022Publication date: October 26, 2023Inventors: Ryan L. Meyer, Vinay Nair, Andrea Gotti, Kevin Shea, Kyle R. Knori
-
Publication number: 20230345708Abstract: Methods, apparatuses, and systems related to a sense line and cell contact for a semiconductor structure are described. An example apparatus includes a first source/drain region and a second source/drain region, where the first source/drain region and the second source/drain region are separated by a channel, a gate opposing the channel, a sense line material coupled to the first source/drain region by a cell contact, where the cell contact is made from a combination of a first polysilicon material and a second polysilicon material, and a storage node coupled to the second source/drain region.Type: ApplicationFiled: April 26, 2022Publication date: October 26, 2023Inventors: Kuo-Chen Wang, Terrence B. McDaniel, Russell A. Benson, Vinay Nair
-
Patent number: 11563008Abstract: Some embodiments include an integrated assembly having digit-line-contact-regions between pairs of capacitor-contact-regions. The capacitor-contact-regions are arranged with six adjacent capacitor-contact-regions in a substantially rectangular configuration. Conductive plugs are coupled with the capacitor-contact-regions. Conductive redistribution material is coupled with the conductive plugs. Upper surfaces of the conductive redistribution material are arranged in a substantially hexagonal-close-packed configuration. Digit lines are over the digit-line-contact-regions. Insulative regions are between the digit lines and the conductive plugs. The insulative regions contain voids and/or low-k dielectric material. Capacitors are coupled with the upper surfaces of the conductive redistribution material.Type: GrantFiled: March 8, 2021Date of Patent: January 24, 2023Assignee: Micron Technology, Inc.Inventors: Guangjun Yang, Vinay Nair, Devesh Dadhich Shreeram, Ashwin Panday, Kangle Li, Zhiqiang Xie, Silvia Borsari, Mohd Kamran Akhtar, Si-Woo Lee
-
Patent number: 11563011Abstract: A method used in forming integrated circuitry comprises forming conductive material over a substrate. The conductive material is patterned into a conductive line that is horizontally longitudinally elongated. The conductive material is vertically recessed in longitudinally-spaced first regions of the conductive line to form longitudinally-spaced conductive pillars that individually are in individual longitudinally-spaced second regions that longitudinally-alternate with the longitudinally-spaced first regions along the conductive line. The conductive pillars project vertically relative to the conductive material in the longitudinally-spaced and vertically-recessed first regions of the conductive line. Electronic components are formed directly above the conductive pillars. Individual of the electronic components are directly electrically coupled to individual of the conductive pillars. Additional methods, including structure independent of method, are disclosed.Type: GrantFiled: September 30, 2020Date of Patent: January 24, 2023Assignee: Micron Technology, Inc.Inventors: Vinay Nair, Silvia Borsari, Ryan L. Meyer, Russell A. Benson, Yi Fang Lee
-
Publication number: 20220358971Abstract: Some embodiments include an integrated assembly having first and second source/drain regions laterally offset from one another. Metal silicide is adjacent to lateral surfaces of the source/drain regions. Metal is adjacent to the metal silicide. Container-shaped first and second capacitor electrodes are coupled to the source/drain regions through the metal silicide and the metal. Capacitor dielectric material lines interior surfaces of the container-shaped first and second capacitor electrodes, A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends into the lined first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: February 10, 2022Publication date: November 10, 2022Applicant: Micron Technology, Inc.Inventors: Che-Chi Lee, Terrence B. McDaniel, Kehao Zhang, Albert P. Chan, Clement Jacob, Luca Fumagalli, Vinay Nair
-
Publication number: 20220285357Abstract: Some embodiments include an integrated assembly having digit-line-contact-regions between pairs of capacitor-contact-regions. The capacitor-contact-regions are arranged with six adjacent capacitor-contact-regions in a substantially rectangular configuration. Conductive plugs are coupled with the capacitor-contact-regions. Conductive redistribution material is coupled with the conductive plugs. Upper surfaces of the conductive redistribution material are arranged in a substantially hexagonal-close-packed configuration. Digit lines are over the digit-line-contact-regions. Insulative regions are between the digit lines and the conductive plugs. The insulative regions contain voids and/or low-k dielectric material. Capacitors are coupled with the upper surfaces of the conductive redistribution material.Type: ApplicationFiled: March 8, 2021Publication date: September 8, 2022Applicant: Micron Technology, Inc.Inventors: Guangjun Yang, Vinay Nair, Devesh Dadhich Shreeram, Ashwin Panday, Kangle Li, Zhiqiang Xie, Silvia Borsari, Mohd Kamran Akhtar, Si-Woo Lee
-
Publication number: 20220147515Abstract: Systems and methods for implementing a multi-factor financial ontology framework are disclosed. In exemplary embodiments, a computer-implement method executing on a computer receives a natural language query from a user device and parses the query to determine a set of natural language terms associated with financial product criteria. The computer system maps the natural language terms to data nodes that implement the financial ontology framework and identifies responsive financial products from those data nodes. The computer system transmits the data corresponding to the responsive financial product to the user device.Type: ApplicationFiled: November 5, 2021Publication date: May 12, 2022Inventors: Vinay Nair, Aniket Vijaykumar Jain
-
Patent number: 11309315Abstract: Systems, methods, and apparatuses are provided for digit line formation for horizontally oriented access devices.Type: GrantFiled: July 30, 2020Date of Patent: April 19, 2022Assignee: Micron Technology, Inc.Inventors: Terrence B. McDaniel, Si-Woo Lee, Vinay Nair, Luca Fumagalli
-
Publication number: 20220102348Abstract: A method used in forming integrated circuitry comprises forming conductive material over a substrate. The conductive material is patterned into a conductive line that is horizontally longitudinally elongated. The conductive material is vertically recessed in longitudinally-spaced first regions of the conductive line to form longitudinally-spaced conductive pillars that individually are in individual longitudinally-spaced second regions that longitudinally-alternate with the longitudinally-spaced first regions along the conductive line. The conductive pillars project vertically relative to the conductive material in the longitudinally-spaced and vertically-recessed first regions of the conductive line. Electronic components are formed directly above the conductive pillars. Individual of the electronic components are directly electrically coupled to individual of the conductive pillars. Additional methods, including structure independent of method, are disclosed.Type: ApplicationFiled: September 30, 2020Publication date: March 31, 2022Applicant: Micron Technology, Inc.Inventors: Vinay Nair, Silvia Borsari, Ryan L. Meyer, Russell A. Benson, Yi Fang Lee
-
Patent number: 11282548Abstract: Some embodiments include an integrated assembly having first and second source/drain regions laterally offset from one another. Metal silicide is adjacent to lateral surfaces of the source/drain regions. Metal is adjacent to the metal silicide. Container-shaped first and second capacitor electrodes are coupled to the source/drain regions through the metal silicide and the metal. Capacitor dielectric material lines interior surfaces of the container-shaped first and second capacitor electrodes, A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends into the lined first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: May 4, 2021Date of Patent: March 22, 2022Assignee: Micron Technology, Inc.Inventors: Che-Chi Lee, Terrence B. McDaniel, Kehao Zhang, Albert P. Chan, Clement Jacob, Luca Fumagalli, Vinay Nair
-
Publication number: 20220059469Abstract: A method of forming a microelectronic device comprises forming a conductive shielding material over a conductive shielding structure and a first dielectric structure horizontally adjacent the conductive shielding structure. A second dielectric structure is formed on first dielectric structure and horizontally adjacent the conductive shielding material. The conductive shielding material and the second dielectric structure are patterned to form fin structures extending in parallel in a first horizontal direction. Each of the fin structures comprises two dielectric end structures integral with remaining portions of the second dielectric structure, and an additional conductive shielding structure interposed between the two dielectric end structures in the first horizontal direction. Conductive lines are formed to extend in parallel in the first horizontal direction and to horizontally alternate with the fin structures in a second horizontal direction orthogonal to the first horizontal direction.Type: ApplicationFiled: August 21, 2020Publication date: February 24, 2022Inventors: Russell A. Benson, Davide Colombo, Yan Li, Terrence B. McDaniel, Vinay Nair, Silvia Borsari
-
Patent number: 11257766Abstract: A method of forming a microelectronic device comprises forming a conductive shielding material over a conductive shielding structure and a first dielectric structure horizontally adjacent the conductive shielding structure. A second dielectric structure is formed on first dielectric structure and horizontally adjacent the conductive shielding material. The conductive shielding material and the second dielectric structure are patterned to form fin structures extending in parallel in a first horizontal direction. Each of the fin structures comprises two dielectric end structures integral with remaining portions of the second dielectric structure, and an additional conductive shielding structure interposed between the two dielectric end structures in the first horizontal direction. Conductive lines are formed to extend in parallel in the first horizontal direction and to horizontally alternate with the fin structures in a second horizontal direction orthogonal to the first horizontal direction.Type: GrantFiled: August 21, 2020Date of Patent: February 22, 2022Assignee: Micron Technology, Inc.Inventors: Russell A. Benson, Davide Colombo, Yan Li, Terrence B. McDaniel, Vinay Nair, Silvia Borsari
-
Publication number: 20220037334Abstract: Systems, methods, and apparatuses are provided for digit line formation for horizontally oriented access devices.Type: ApplicationFiled: July 30, 2020Publication date: February 3, 2022Inventors: Terrence B. McDaniel, Si-Woo Lee, Vinay Nair, Luca Fumagalli
-
Patent number: 11189484Abstract: Methods, apparatuses, and systems related to a semiconductor nitridation passivation are described. An example method includes performing a dry etch process on a semiconductor structure on a wafer in a semiconductor fabrication process. The method further includes performing a dry strip process on the semiconductor structure. The method further includes performing a first wet strip clean process on the semiconductor. The method further includes performing a second wet strip clean process on the semiconductor. The method further includes performing a nitridation passivation on the semiconductor structure to avoid oxidization of the semiconductor structure. The method further performing a spacer material deposition on the semiconductor structure.Type: GrantFiled: December 20, 2019Date of Patent: November 30, 2021Assignee: Micron Technology, Inc.Inventors: Russell A. Benson, Silvia Borsari, Vinay Nair, Ying Rui, Somik Mukherjee
-
Patent number: 11094697Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.Type: GrantFiled: November 7, 2018Date of Patent: August 17, 2021Assignee: Micron Technology, Inc.Inventors: Gloria Yang, Suraj J. Mathew, Raghunath Singanamalla, Vinay Nair, Scott J. Derner, Michael Amiel Shore, Brent Keeth, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
-
Publication number: 20210193460Abstract: Methods, apparatuses, and systems related to a semiconductor nitridation passivation are described. An example method includes performing a dry etch process on a semiconductor structure on a wafer in a semiconductor fabrication process. The method further includes performing a dry strip process on the semiconductor structure. The method further includes performing a first wet strip clean process on the semiconductor. The method further includes performing a second wet strip clean process on the semiconductor. The method further includes performing a nitridation passivation on the semiconductor structure to avoid oxidization of the semiconductor structure. The method further performing a spacer material deposition on the semiconductor structure.Type: ApplicationFiled: December 20, 2019Publication date: June 24, 2021Inventors: Russell A. Benson, Silvia Borsari, Vinay Nair, Ying Rui, Somik Mukherjee