Patents by Inventor Vinay Raghav
Vinay Raghav has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11940855Abstract: Three components are used to adjust the CPU peak power based on the USB TYPE-C device states. These components include operating system (OS) Peak Power Manager, USB TYPE-C Connector Manager, and USB TYPE-C Protocol Device Driver. The USB TYPE-C Connector Manager sends a synchronous request to the OS Peak Power Manager when a USB TYPE-C power sink device is attached or detached, and the USB TYPE-C Protocol Device Driver sends a synchronous request to the Peak Power Manager when the power sink transitions device state. The Peak Power Manager takes power budget from the CPU when the USB TYPE-C connector is attached to a power sink and is active (e.g., high power device state), and gives back the power budget to the CPU for performance when the USB TYPE-C connector is either detached or the attached and power sink device is idle (lowest device state).Type: GrantFiled: October 12, 2020Date of Patent: March 26, 2024Assignee: Intel CorporationInventors: Ashwin Umapathy, Chee Lim Nge, Timothy Smith, Dmitriy Berchanskiy, Vinay Raghav
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Publication number: 20230103000Abstract: Embodiments of apparatuses, methods, and systems for hardware manage address translation services are described. In an embodiment, an apparatus includes a first interconnect, a second interconnect, address translation hardware, a device, a translation lookaside buffer. The address translation hardware is coupled to the interconnect and is to provide a translation of a first address to a second address. The device is coupled to the first interconnect and the second interconnect and is to provide the first address to the address translation hardware through the first interconnect. The translation lookaside buffer includes an entry to store the translation, which is to be provided to the translation lookaside buffer through the first interconnect by the address translation hardware. The device is to access a system memory through the second interconnect using the second address from the entry in the translation lookaside buffer.Type: ApplicationFiled: September 25, 2021Publication date: March 30, 2023Applicant: Intel CorporationInventors: Rupin Vakharwala, Prashant Sethi, Rajesh M. Sankaran, Philip R. Lantz, David J. Harriman, Utkarsh Y. Kakaiya, Vinay Raghav, Ashok Raj, Siva Bhanu Krishna Boga
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Publication number: 20230077239Abstract: Device virtualization techniques can enable physical I/O devices (such as PCIe devices or other I/O devices) to appear as virtual I/O devices, while also enabling selective exposure of information regarding the physical I/O devices to enable the native drivers of the physical I/O devices to be run. In one example, one or more physical I/O devices associated with a virtual I/O device are locked, and an interface is monitored for requests to those physical I/O devices. The device can be unlocked in response to a request to a predetermined address. When a physical I/O device is locked, read requests to read an identifier of the physical device are blocked, and a value associated with the virtual I/O device is provided. When the physical I/O device is unlocked, read requests to read an identifier of the physical I/O device are forwarded to the physical I/O device.Type: ApplicationFiled: November 11, 2022Publication date: March 9, 2023Inventors: Filip SCHMOLE, Ryan HOLMQVIST, Kapil KARKRA, Orden SMITH, Nicholas ADAMS, Vinay RAGHAV
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Patent number: 11550746Abstract: A device includes a plurality of ports and a plurality of capability registers that correspond to a respective one of the plurality of ports. The device is to connect to one or more processors of a host device through the plurality of ports, and each of the plurality of ports comprises a respective protocol stack to support a respective link between the corresponding port and the host device according to a particular interconnect protocol. Each of the plurality of capability registers comprises a respective set of fields for use in configuration of the link between its corresponding port and one of the one or more processors of the host device. The fields include a field to indicate an association between the port and a particular processor, a field to indicate a port identifier for the port, and a field to indicate a total number of ports of the device.Type: GrantFiled: December 26, 2019Date of Patent: January 10, 2023Assignee: Intel CorporationInventors: Vinay Raghav, David J. Harriman, Utkarsh Y. Kakaiya
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Patent number: 11513808Abstract: Automatic-switching and deployment of software (SW)- or firmware (FW)-based USB4 connection managers (CMs) and associated methods, apparatus, software and firmware. A handshake is defined between BIOS and an operating system (OS) to discover supported CM capability and dynamically switch from a FW CM to a SW CM and visa verse if there is a mismatch. In addition, a mechanism is defined to deploy the correct FW or SW CM driver based on class code, 2-part or 4-part ID. Support for continued USB4 operation during an OS upgrade or downgrade is provided, while ensuring that the best possible CM solution is used based on the advertised platform and OS capability. USB4 controllers support a pass-through mode under which the host controller FW redirects control packets sent between an SW CM and a USB4 fabric, and a FW CM mode under which control packets are communicated between the host controller FW and the USB4 fabric to configure USB4 peripheral devices and/or USB4 hubs in the USB4 fabric.Type: GrantFiled: June 28, 2019Date of Patent: November 29, 2022Assignee: Intel CorporationInventors: Vinay Raghav, Prashant Sethi, Robert Gough, Reuven Rozic, Uri Soloveychik
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Publication number: 20220164303Abstract: Methods, apparatus, systems, and articles of manufacture to manage memory in a computing apparatus are disclosed. Methods, apparatus, systems, and articles of manufacture to optimize or improve buffer invalidation to reduce memory management performance overhead are disclosed. An example apparatus includes an input-output memory management unit (IOMMU) circuitry to control access to memory circuitry, the IOMMU circuitry to increment a counter from a first value to a second value when a memory access to a location in the memory circuitry is allocated and to decrement the counter from the second value to the first value when the memory access to the location in the memory circuitry is deallocated; and an operating system (OS) memory manager to enable reallocation of the location in the memory circuitry when the counter is at the first value.Type: ApplicationFiled: November 24, 2021Publication date: May 26, 2022Inventors: Vinay Raghav, Yesha Shah, Paras Goyal, Utkarsh Y. Kakaiya
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Patent number: 11157068Abstract: Embodiments may include systems and methods for communication including a communication port with a first lane and a second lane, a first power controller and a second power controller coupled to the communication port. The first power controller is to control, at a first time instance, the first lane to operate in a first power state selected from a first set of power states for the first lane. The second power controller is to control, at a second time instance, the second lane to operate in a second power state selected from a second set of power states for the second lane, wherein the first power state is different from the second power state. Other embodiments may be described and/or claimed.Type: GrantFiled: January 25, 2019Date of Patent: October 26, 2021Assignee: Intel CorporationInventors: Dmitriy Berchanskiy, Vinay Raghav, Udaya Natarajan, Huimin Chen
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Patent number: 11106474Abstract: Aspects of the embodiments include systems, methods, devices, and computer program products to receive, from the downstream component, an indication of an extended capability; determining, from the indication, one or more configuration parameters for the downstream component; applying the one or more configuration parameters; and performing data signal or control signal transmissions across the PCIe-compliant link with the downstream component based, at least in part, on the applied one or more configuration parameters. The extended capabilities can be indicated by a DVSEC extended capability definition received from a downstream device. The extended capabilities of the downstream component can indicate the number of buses, the port type, the expandability capability, the D3Cold support status, the host router indicator, and/or the safe eject requirements of the downstream component.Type: GrantFiled: January 27, 2020Date of Patent: August 31, 2021Assignee: Intel CorporationInventors: Vinay Raghav, Reuven Rozic, David J. Harriman
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Publication number: 20210109578Abstract: Three components are used to adjust the CPU peak power based on the USB TYPE-C device states. These components include operating system (OS) Peak Power Manager, USB TYPE-C Connector Manager, and USB TYPE-C Protocol Device Driver. The USB TYPE-C Connector Manager sends a synchronous request to the OS Peak Power Manager when a USB TYPE-C power sink device is attached or detached, and the USB TYPE-C Protocol Device Driver sends a synchronous request to the Peak Power Manager when the power sink transitions device state. The Peak Power Manager takes power budget from the CPU when the USB TYPE-C connector is attached to a power sink and is active (e.g., high power device state), and gives back the power budget to the CPU for performance when the USB TYPE-C connector is either detached or the attached and power sink device is idle (lowest device state).Type: ApplicationFiled: October 12, 2020Publication date: April 15, 2021Applicant: Intel CorporationInventors: Ashwin Umapathy, Chee Lim Nge, Timothy Smith, Dmitriy Berchanskiy, Vinay Raghav
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Publication number: 20200319898Abstract: Aspects of the embodiments include systems, methods, devices, and computer program products to receive, from the downstream component, an indication of an extended capability; determining, from the indication, one or more configuration parameters for the downstream component; applying the one or more configuration parameters; and performing data signal or control signal transmissions across the PCIe-compliant link with the downstream component based, at least in part, on the applied one or more configuration parameters. The extended capabilities can be indicated by a DVSEC extended capability definition received from a downstream device. The extended capabilities of the downstream component can indicate the number of buses, the port type, the expandability capability, the D3Cold support status, the host router indicator, and/or the safe eject requirements of the downstream component.Type: ApplicationFiled: January 27, 2020Publication date: October 8, 2020Applicant: Intel CorporationInventors: Vinay Raghav, Reuven Rozic, David J. Harriman
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Publication number: 20200210363Abstract: A device includes a plurality of ports and a plurality of capability registers that correspond to a respective one of the plurality of ports. The device is to connect to one or more processors of a host device through the plurality of ports, and each of the plurality of ports comprises a respective protocol stack to support a respective link between the corresponding port and the host device according to a particular interconnect protocol. Each of the plurality of capability registers comprises a respective set of fields for use in configuration of the link between its corresponding port and one of the one or more processors of the host device. The fields include a field to indicate an association between the port and a particular processor, a field to indicate a port identifier for the port, and a field to indicate a total number of ports of the device.Type: ApplicationFiled: December 26, 2019Publication date: July 2, 2020Applicant: Intel CorporationInventors: Vinay Raghav, David J. Harriman, Utkarsh Y. Kakaiya
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Patent number: 10545773Abstract: Aspects of the embodiments include systems, methods, devices, and computer program products to receive, from the downstream component, an indication of an extended capability; determining, from the indication, one or more configuration parameters for the downstream component; applying the one or more configuration parameters; and performing data signal or control signal transmissions across the PCIe-compliant link with the downstream component based, at least in part, on the applied one or more configuration parameters. The extended capabilities can be indicated by a DVSEC extended capability definition received from a downstream device. The extended capabilities of the downstream component can indicate the number of buses, the port type, the expandability capability, the D3Cold support status, the host router indicator, and/or the safe eject requirements of the downstream component.Type: GrantFiled: May 23, 2018Date of Patent: January 28, 2020Assignee: Intel CorporationInventors: Vinay Raghav, Reuven Rozic, David J. Harriman
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Patent number: 10521388Abstract: A device includes a plurality of ports and a plurality of capability registers that correspond to a respective one of the plurality of ports. The device is to connect to one or more processors of a host device through the plurality of ports, and each of the plurality of ports comprises a respective protocol stack to support a respective link between the corresponding port and the host device according to a particular interconnect protocol. Each of the plurality of capability registers comprises a respective set of fields for use in configuration of the link between its corresponding port and one of the one or more processors of the host device. The fields include a field to indicate an association between the port and a particular processor, a field to indicate a port identifier for the port, and a field to indicate a total number of ports of the device.Type: GrantFiled: September 28, 2018Date of Patent: December 31, 2019Assignee: Intel CorporationInventors: Vinay Raghav, David J. Harriman, Utkarsh Y. Kakaiya
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Publication number: 20190317774Abstract: Automatic-switching and deployment of software (SW)- or firmware (FW)-based USB4 connection managers (CMs) and associated methods, apparatus, software and firmware. A handshake is defined between BIOS and an operating system (OS) to discover supported CM capability and dynamically switch from a FW CM to a SW CM and visa verse if there is a mismatch. In addition, a mechanism is defined to deploy the correct FW or SW CM driver based on class code, 2-part or 4-part ID. Support for continued USB4 operation during an OS upgrade or downgrade is provided, while ensuring that the best possible CM solution is used based on the advertised platform and OS capability. USB4 controllers support a pass-through mode under which the host controller FW redirects control packets sent between an SW CM and a USB4 fabric, and a FW CM mode under which control packets are communicated between the host controller FW and the USB4 fabric to configure USB4 peripheral devices and/or USB4 hubs in the USB4 fabric.Type: ApplicationFiled: June 28, 2019Publication date: October 17, 2019Inventors: Vinay Raghav, Prashant Sethi, Robert Gough, Reuven Rozic, Uri Soloveychik
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Publication number: 20190155361Abstract: Embodiments may include systems and methods for communication including a communication port with a first lane and a second lane, a first power controller and a second power controller coupled to the communication port. The first power controller is to control, at a first time instance, the first lane to operate in a first power state selected from a first set of power states for the first lane. The second power controller is to control, at a second time instance, the second lane to operate in a second power state selected from a second set of power states for the second lane, wherein the first power state is different from the second power state. Other embodiments may be described and/or claimed.Type: ApplicationFiled: January 25, 2019Publication date: May 23, 2019Inventors: Dmitriy Berchanskiy, Vinay Raghav, Udaya Natarajan, Huimin Chen
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Publication number: 20190042508Abstract: A device includes a plurality of ports and a plurality of capability registers that correspond to a respective one of the plurality of ports. The device is to connect to one or more processors of a host device through the plurality of ports, and each of the plurality of ports comprises a respective protocol stack to support a respective link between the corresponding port and the host device according to a particular interconnect protocol. Each of the plurality of capability registers comprises a respective set of fields for use in configuration of the link between its corresponding port and one of the one or more processors of the host device. The fields include a field to indicate an association between the port and a particular processor, a field to indicate a port identifier for the port, and a field to indicate a total number of ports of the device.Type: ApplicationFiled: September 28, 2018Publication date: February 7, 2019Applicant: Intel CorporationInventors: Vinay Raghav, David J. Harriman, Utkarsh Y. Kakaiya
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Publication number: 20190042281Abstract: Aspects of the embodiments include systems, methods, devices, and computer program products to receive, from the downstream component, an indication of an extended capability; determining, from the indication, one or more configuration parameters for the downstream component; applying the one or more configuration parameters; and performing data signal or control signal transmissions across the PCIe-compliant link with the downstream component based, at least in part, on the applied one or more configuration parameters. The extended capabilities can be indicated by a DVSEC extended capability definition received from a downstream device. The extended capabilities of the downstream component can indicate the number of buses, the port type, the expandability capability, the D3Cold support status, the host router indicator, and/or the safe eject requirements of the downstream component.Type: ApplicationFiled: May 23, 2018Publication date: February 7, 2019Inventors: Vinay Raghav, Reuven Rozic, David J. Harriman