Patents by Inventor Vinay Srinivas

Vinay Srinivas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12260311
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for processing inputs using a neural network system that includes one or more pre-normalized layers or one or more regularization normalization layers.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: March 25, 2025
    Assignee: Google LLC
    Inventors: Jascha Narain Sohl-Dickstein, Vinay Srinivas Rao
  • Publication number: 20220108149
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for processing inputs using a neural network system that includes one or more pre-normalized layers or one or more regularization normalization layers.
    Type: Application
    Filed: October 4, 2021
    Publication date: April 7, 2022
    Inventors: Jascha Narain Sohl-Dickstein, Vinay Srinivas Rao
  • Patent number: 7222311
    Abstract: A method and an apparatus are provided for post-layout optimization of an integrated circuit. In one instance, only local transformations accomplished by incremental changes to placement and routing are provided, so as to avoid the costly design iteration loop that requires re-synthesis, re-place and re-route. Optimization can be provided in multiple optimization phases each accomplishing a specified set of transformations. Static timing analysis is performed at the end of each set of local transformations to determine if further optimization steps are required. In one instance, the physical design is first scanned for mismatch between drivers and loads. Then, in a second optimization phase, “hot spots” in the physical design are identified for local transformation using a “bidirectional combinational total negative slack” (BCTNS) algorithm. In subsequent phases, optimization based on meeting setup times and hold times in a critical path are performed.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: May 22, 2007
    Assignee: Sequence Design, Inc.
    Inventors: Douglas Kaufman, Hazem Almusa, Vinay Srinivas, Donald V. Organ, Larry Ke, Wei Li, Japinder Singh, Robert Mathews
  • Publication number: 20030177455
    Abstract: A method and an apparatus are provided for post-layout optimization of an integrated circuit. In one instance, only local transformations accomplished by incremental changes to placement and routing are provided, so as to avoid the costly design iteration loop that requires re-synthesis, re-place and re-route. Optimization can be provided in multiple optimization phases each accomplishing a specified set of transformations. Static timing analysis is performed at the end of each set of local transformations to determine if further optimization steps are required. In one instance, the physical design is first scanned for mismatch between drivers and loads. Then, in a second optimization phase, “hot spots” in the physical design are identified for local transformation using a “bidirectional combinational total negative slack” (BCTNS) algorithm. In subsequent phases, optimization based on meeting setup times and hold times in a critical path are performed.
    Type: Application
    Filed: March 12, 2003
    Publication date: September 18, 2003
    Applicant: Sequence Design, Inc.
    Inventors: Douglas Kaufman, Hazem Almusa, Vinay Srinivas, Donald V. Organ, Larry Ke, Wei Li, Japinder Singh, Robert Mathews
  • Patent number: 6591407
    Abstract: A method and an apparatus are provided for post-layout optimization of an integrated circuit. In one instance, only local transformations accomplished by incremental changes to placement and routing are provided, so as to avoid the costly design iteration loop that requires re-synthesis, re-place and re-route. Optimization can be provided in multiple optimization phases each accomplishing a specified set of transformations. Static timing analysis is performed at the end of each set of local transformations to determine if further optimization steps are required. In one instance, the physical design is first scanned for mismatch between drivers and loads. Then, in a second optimization phase, “hot spots” in the physical design are identified for local transformation using a “bidirectional combinational total negative slack” (BCTNS) algorithm. In subsequent phases, optimization based on meeting setup times and hold times in a critical path are performed.
    Type: Grant
    Filed: March 1, 2000
    Date of Patent: July 8, 2003
    Assignee: Sequence Design, Inc.
    Inventors: Douglas Kaufman, Hazem Almusa, Vinay Srinivas, Donald V. Organ, Larry Ke, Wei Li, Japinder Singh, Robert Mathews