Abstract: The present invention discloses a continuous process for the synthesis of dimethyl carbonate from methanol and carbon dioxide over a ceria-based mixed metal oxide-silica catalyst formulation in the presence of a dehydrating or water trapping compound (2-Cyanopyridine).

Abstract: The present disclosure generally relates to displaying a user interface for sharing an account associated with a first user identity with a second user identity. The user interface includes a first sharing option and a second sharing option. One or more inputs corresponding to a request to share the account are detected. If the one or more inputs include a selection of the first sharing option, a request to invite the second user identity to become a joint owner of the account is transmitted. If the one or more inputs include a selection of the second sharing option, a request to invite the second user identity to become a participant of the account without becoming a joint owner of the account is transmitted.

Abstract: We describe herein a high voltage semiconductor device comprising a power semiconductor device portion (100) and a temperature sensing device portion (185). The temperature sensing device portion comprises: an anode region (140), a cathode region (150), a body region (160) in which the anode region and the cathode region are formed. The temperature sensing device portion also comprises a semiconductor isolation region (165) in which the body region is formed, the semiconductor isolation region having an opposite conductivity type to the body region, the semiconductor isolation region being formed between the power semiconductor device portion and the temperature sensing device portion.

Abstract: A clock generation circuit for generating a plurality of output clocks includes: a differential circuit for receiving a single input clock signal and outputting two differential clock signals, and a DC signal; a first polyphase filter for generating four clock signals from the differential clock signals which are a quadrature phase apart from each other; a plurality of setting buffers for setting a same DC point for the four clock signals and generating four resultant clock signals; coupled polyphase filters for generating four more clock signals which are a quadrature apart from each other, and outputting the resultant eight clock signals; a phase mixer, for generating eight output clock signals 45 degrees apart from each other; and a plurality of restoration buffers for setting a DC point for each of the eight clock signals and generating eight output clock signals all riding on a same DC point.

Abstract: We describe herein a high voltage semiconductor device comprising a power semiconductor device portion (100) and a temperature sensing device portion (185). The temperature sensing device portion comprises: an anode region (140), a cathode region (150), a body region (160) in which the anode region and the cathode region are formed. The temperature sensing device portion also comprises a semiconductor isolation region (165) in which the body region is formed, the semiconductor isolation region having an opposite conductivity type to the body region, the semiconductor isolation region being formed between the power semiconductor device portion and the temperature sensing device portion.

Abstract: A high-voltage semiconductor device includes a semiconductor substrate having a first conductivity type, a source region and a drain region disposed on the semiconductor substrate. The drain region has a second conductivity type that is the opposite of the first conductivity type, and the source region includes a part having the first conductivity type and another part having the second conductivity type. The device includes a first and a second isolation structures disposed on two opposite sides of the drain region. The first isolation structure is between the source and the drain region. The device includes a first well region disposed below the second isolation structure. The top surface of the first well region is adjacent to the bottom surface of the second isolation structure. In addition, the device includes a first buried layer disposed in the semiconductor substrate and that overlaps the first well region.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type; a deep well region disposed on the semiconductor substrate, and having a second conductivity type opposite to the first conductivity type; a first well region and a second well region disposed in the deep well region and having the first conductivity type, wherein the first well region and the second well region are separated by a portion of the deep well region, and the first well region is electrically connected to the second well region; and a first doped region and a second doped region disposed in the deep well region and having the second conductivity type, wherein the first well region and the second well region are located between the first doped region and the second doped region.

Abstract: A semiconductor device includes a substrate having a first conductive type. An epitaxial layer having a second conductive type is disposed on the substrate. A first buried layer of the second conductive type is disposed within a high side region of the substrate. A second buried layer of the second conductive type is disposed directly above the first buried layer of the second conductive type. A top surface of the first buried layer of the second conductive type and a top surface of the second buried layer of the second conductive type are apart from a top surface of the epitaxial layer by different distances. A dopant concentration of the first buried layer of the second conductive type is less than that of the second buried layer of the second conductive type.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type; a deep well region disposed on the semiconductor substrate, and having a second conductivity type opposite to the first conductivity type; a first well region and a second well region disposed in the deep well region and having the first conductivity type, wherein the first well region and the second well region are separated by a portion of the deep well region, and the first well region is electrically connected to the second well region; and a first doped region and a second doped region disposed in the deep well region and having the second conductivity type, wherein the first well region and the second well region are located between the first doped region and the second doped region.

Abstract: A high-voltage semiconductor device includes a semiconductor substrate having a first conductivity type, a source region and a drain region disposed on the semiconductor substrate. The drain region has a second conductivity type that is the opposite of the first conductivity type, and the source region includes a part having the first conductivity type and another part having the second conductivity type. The device includes a first and a second isolation structures disposed on two opposite sides of the drain region. The first isolation structure is between the source and the drain region. The device includes a first well region disposed below the second isolation structure. The top surface of the first well region is adjacent to the bottom surface of the second isolation structure. In addition, the device includes a first buried layer disposed in the semiconductor substrate and that overlaps the first well region.

Abstract: A transient-voltage-suppression (TVS) diode device and a method of fabricating the same are disclosed. The TVS diode device includes a substrate. A second conductivity type first epitaxial layer is disposed over the substrate. A second conductivity type second epitaxial layer is disposed between the second conductivity type first epitaxial layer and the substrate. A plurality of trench isolation features divides the substrate into a first active region including a second conductivity type doped well region disposed in the second conductivity type first epitaxial layer. A first conductivity type doped well region and a first conductivity type buried layer are disposed in the second conductivity type second epitaxial layer. The second conductivity type doped well region and the first conductivity type buried layer collectively form a Zener diode.

Abstract: Provided are a diode, a junction field effect transistor (JFET), and a semiconductor device that have a top doped region. A dopant concentration gradient of the top doped region at one side is different from the dopant concentration gradient of the top doped region at an opposite side. The top doped region is able to increase a breakdown voltage of the device and decrease an on-state resistance (Ron) of the device.

Abstract: A semiconductor device includes a substrate having a first conductive type. An epitaxial layer having a second conductive type is disposed on the substrate. A first buried layer of the second conductive type is disposed within a high side region of the substrate. A second buried layer of the second conductive type is disposed directly above the first buried layer of the second conductive type. A top surface of the first buried layer of the second conductive type and a top surface of the second buried layer of the second conductive type are apart from a top surface of the epitaxial layer by different distances. A dopant concentration of the first buried layer of the second conductive type is less than that of the second buried layer of the second conductive type.

Abstract: A transient-voltage-suppression (TVS) diode device and a method of fabricating the same are disclosed. The TVS diode device includes a substrate. A second conductivity type first epitaxial layer is disposed over the substrate. A second conductivity type second epitaxial layer is disposed between the second conductivity type first epitaxial layer and the substrate. A plurality of trench isolation features divides the substrate into a first active region including a second conductivity type doped well region disposed in the second conductivity type first epitaxial layer. A first conductivity type doped well region and a first conductivity type buried layer are disposed in the second conductivity type second epitaxial layer. The second conductivity type doped well region and the first conductivity type buried layer collectively form a Zener diode.

Abstract: Provided are a diode, a junction field effect transistor (JFET), and a semiconductor device that have a top doped region. A dopant concentration gradient of the top doped region at one side is different from the dopant concentration gradient of the top doped region at an opposite side. The top doped region is able to increase a breakdown voltage of the device and decrease an on-state resistance (Ron) of the device.