Patents by Inventor Vinaya K. Singh

Vinaya K. Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Transformation of simple subset of PSL into SERE implication formulas for verification with model checking and simulation engines using semantic preserving rewrite rules
    Patent number: 7386813
    Abstract: The disclosure presents a formulation to support simulatable subset (also known as ‘simple-subset’) of a property specification language. This method is applicable for model checking and simulation. In this formulation, the ‘simple-subset’ is transformed to a set of basic formulas. Verification engines are required to support the basic formula only. The basic formula is a form of automata in the property specification language. This is called SERE implication. The efficiency of verification is dependent on size of automata. Miscellaneous opportunistic rules are applied to optimize SERE implication formulas.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: June 10, 2008
    Assignee: Cadence Design Systems, Inc.
    Inventors: Vinaya K. Singh, Tarun Garg