Abstract: The disclosure provides biodegradable implantable devices such as a stent comprising a biodegradable polymeric material wherein the polymeric material is treated to control crystallinity and/or Tg. The stent is capable of expanding at body temperature in a body lumen from a crimped configuration to a deployed diameter and will have sufficient strength to support a body lumen when expanded.

Abstract: Aspects of a storage device are provided which delay thermal throttling in response to temperature increases based on different reliable temperatures for different types of cells, such as SLCs, hybrid SLCs and MLCs. Initially, a controller writes first data to a block of MLCs at a first data rate when a temperature of the block meets a first temperature threshold for MLCs. Subsequently, the controller writes second data to the block at a second data rate lower than the first data rate when the temperature of the block meets a second temperature threshold for SLCs. For hybrid SLCs, the MLCs are each configured to store a first number of bits, and the controller writes a second number of bits smaller than the first number of bits in each of one or more of the cells. Storage device performance is thus improved through delayed thermal throttling without compromising data integrity.

Abstract: The present disclosure generally relates to using irregular MetaBlocks (IRMBs) in both host and control pools. The IRMBs are used to ensure efficient wear leveling. Blocks in the control pool are swapped with blocks in the host pool upon exceeding a program-erase count (PEC) threshold. Additionally, the swapping algorithm for IRMBs can be used to ensure an efficient recovery from an ungraceful shutdown (UGSD) event.

Abstract: A storage device includes multiple memory dies and a controller configured to: (i) perform XOR parity computations for parity bins based, at least in part, on updated contents of a first user data memory cell and contents of each user data memory cell also assigned to the first parity bin, (ii) storing the first parity data into a first parity memory cell associated with the first parity bin; (iii) identify a second parity memory cell for dynamic reconfiguration based, at least in part, on performance data of the non-volatile memory device, the second parity memory cell being assigned to a second parity bin; (iv) copy the second parity memory cell to a third memory cell of the plurality of memory cells; and (v) associate the third memory cell with the second parity bin, thereby making the third memory cell a parity memory cell of the plurality of parity memory cells.

Abstract: Technology is disclosed herein for reducing wear due to erasing and programming non-volatile memory cells. The memory system selects a hybrid SLC group of cells for programming to an SLC mode while the selected hybrid SLC group is presently programmed to either the SLC mode or an MLC mode. Memory cells in the selected hybrid SLC group are erased to an SLC erased state regardless of the presently programmed mode of the selected hybrid SLC group. An average memory cell Vt of the SLC erased state is greater than an average threshold voltage of an MLC erased state. Memory cells in the selected hybrid SLC group are programmed from the SLC erased state to an SLC programmed state. Erasing the hybrid SLC group to the SLC erased state reduces wear relative to erasing to the MLC erased state. Therefore, the useful life of the hybrid SLC group is extended.

Abstract: Technology is disclosed herein for reducing wear due to erasing and programming non-volatile memory cells. The memory system selects a hybrid SLC group of cells for programming to an SLC mode while the selected hybrid SLC group is presently programmed to either the SLC mode or an MLC mode. Memory cells in the selected hybrid SLC group are erased to an SLC erased state regardless of the presently programmed mode of the selected hybrid SLC group. An average memory cell Vt of the SLC erased state is greater than an average threshold voltage of an MLC erased state. Memory cells in the selected hybrid SLC group are programmed from the SLC erased state to an SLC programmed state. Erasing the hybrid SLC group to the SLC erased state reduces wear relative to erasing to the MLC erased state. Therefore, the useful life of the hybrid SLC group is extended.

Abstract: Storage devices include a memory array comprised of a plurality of memory devices. These memory devices are programmed with a modified distribution across the available memory states within the devices. The modified distribution of memory states attempts to minimize the use of memory states that are susceptible to negative effects. These negative effects can include read and write disturbs as well as data retention errors. Often, these negative effects occur on memory states on the lower and upper states within the voltage threshold range of the memory device. The distribution of memory states can be modified though the use of a modified randomization seed configured to change the probabilities of programming of each page within the memory device. This modification of the randomization seed can yield desired distribution of memory device states that are configured to reduce exposure to negative effects thus prolonging the overall lifespan of the storage device.

Abstract: A storage device includes multiple memory dies and a controller configured to: (i) perform XOR parity computations for parity bins based, at least in part, on updated contents of a first user data memory cell and contents of each user data memory cell also assigned to the first parity bin, (ii) storing the first parity data into a first parity memory cell associated with the first parity bin; (iii) identify a second parity memory cell for dynamic reconfiguration based, at least in part, on performance data of the non-volatile memory device, the second parity memory cell being assigned to a second parity bin; (iv) copy the second parity memory cell to a third memory cell of the plurality of memory cells; and (v) associate the third memory cell with the second parity bin, thereby making the third memory cell a parity memory cell of the plurality of parity memory cells.

Abstract: The present disclosure generally relates to using irregular MetaBlocks (IRMBs) in both host and control pools. The IRMBs are used to ensure efficient wear leveling. Blocks in the control pool are swapped with blocks in the host pool upon exceeding a program-erase count (PEC) threshold. Additionally, the swapping algorithm for IRMBs can be used to ensure an efficient recovery from an ungraceful shutdown (UGSD) event.

Abstract: Storage devices are capable of utilizing failed bit count (FBC) reduction devices to reduce FBCs for word lines in blocks. An FBC reduction device may include a FBC count component, a threshold component, a pre-verify component, and a soft program component. The FBC count component may access the FBC for the word line, where the block has unprogrammed word lines in an unprogrammed region separated from programmed word lines of a programmed region by the word line. The threshold component may determine whether the FBC of the word line exceeds a predetermined threshold. When the FBC exceeds the threshold, the pre-verify component may perform pre-verify operations on the programmed region. The soft program component may program the word line with first data equal to second data programmed in a second block. In response to disabling pre-verify operations, the program component may program the unprogrammed word lines in the unprogrammed region.

Abstract: A stent (scaffold) or other luminal prosthesis comprising circumferential structural elements which provide high strength after deployment and allows for scaffold to uncage, and/or allow for scaffold or luminal expansion thereafter. The circumferential scaffold is typically formed from non-degradable material and will be modified to expand and/or uncage after deployment.

Abstract: Storage devices include a memory array comprised of a plurality of memory devices. These memory devices are programmed to store data and erased when data is invalidated. Traditional storage devices waited to erase memory devices until new data was ready to write to them in order to avoid baking in the erase state. However, the act of erasing adds time to the overall program cycle and is getting larger as storage device capacity and complexity increases. Because of newer configurations, the threat of baking in erase states is decreased, allowing memory devices within a memory array to be pre-erased prior to writing. This reduces write times and be dynamically implemented in response to one or more changing conditions. Pre-erasing can be accomplished by utilizing a pre-erase list that can indicate pre-erased memory devices and provide them in response to a write command prior to the use of non-erased memory devices.

Abstract: A stent (scaffold) or other luminal prosthesis comprising circumferential structural elements which provide high strength after deployment and allows for scaffold to uncage, and/or allow for scaffold or luminal expansion thereafter. The circumferential scaffold is typically formed from non-degradable material and will be modified to expand and/or uncage after deployment.

Abstract: A storage device may detect errors during data transfer. Upon detection of one or more data transfer errors, for example, the storage device can begin to scan pages within a plurality of memory devices for uncorrectable error correction codes. Once scanned, a range of pages within the plurality of memory devices with uncorrectable error correction codes associated with a write abort error may be determined. The stage of multi-pass programming achieved on each page within that range is then established. Once calculated, the previously aborted multi-pass programming of each page within the range of pages can continue until completion. Upon completion, normal operations may continue without discarding physical data location.

Abstract: Clot aspiration systems intended for removing clot from a blood vessel include an aspiration assembly which will have two or more of the following components: an aspiration catheter, an inner catheter, an intermediate catheter, and an outer catheter, the latter typically being a guiding or other sheath. A transition structure is coupled to a distal end of the aspiration assembly to cover or fill an open distal end of one or more of the components of the aspiration assembly. The transition structure may be configured to facilitate introduction of the aspiration catheter into the patient's vasculature and/or advancement of the aspiration catheter through the vasculature to a target site, such as a cerebral target site which may be occluded with clot, thrombus, or other occlusive material.

Abstract: A stent (scaffold) or other luminal prosthesis comprising circumferential structural elements which provide high strength after deployment and allows for scaffold to uncage, and/or allow for scaffold or luminal expansion thereafter. The circumferential scaffold is typically formed from non-degradable material and will be modified to expand and/or uncage after deployment.

Abstract: Storage devices include a memory array comprised of a plurality of memory devices. These memory devices are programmed with a modified distribution across the available memory states within the devices. The modified distribution of memory states attempts to minimize the use of memory states that are susceptible to negative effects. These negative effects can include read and write disturbs as well as data retention errors. Often, these negative effects occur on memory states on the lower and upper states within the voltage threshold range of the memory device. The distribution of memory states can be modified though the use of a modified randomization seed configured to change the probabilities of programming of each page within the memory device. This modification of the randomization seed can yield desired distribution of memory device states that are configured to reduce exposure to negative effects thus prolonging the overall lifespan of the storage device.

Abstract: Storage devices include a memory array comprised of a plurality of memory devices arranged in word lines. The word lines are further arranged within memory blocks. When erasing memory blocks, various storage devices may utilize a stripe-erase process that alternates the erasure of word lines within the memory blocks. The stripe-erase process is often carried out in multiple steps. However, an ungraceful shutdown can interrupt the erasing processing between one of these stripe-erase steps. The status of each memory device associated with the aborted erasure needs to be known before operations can continue. Methods and systems described herein properly classify and process memory blocks after an aborted erase command by analyzing both even and odd word lines within each of the memory blocks. By properly categorizing each memory block, overprogramming and other negative effects can be avoided, increasing the overall lifespan of the storage device that utilizes a stripe-erase process.

Abstract: Storage devices may be configured to desirably reduce the time required to perform a physical secure erase operation. The storage device includes a controller that is configured to direct the storage device to receive a physical secure erase command. The storage device can then identify the one or more blocks within the memory array for secure erasure based on the received physical secure erase command. For each block identified for erasure, the storage device further evaluates the block to determine the level type of cells within the block. In response to the cell level type being single-level, a single-cell erase command is issued to perform a single-level cell erase on the block. Conversely, in response to the cell level type being a higher-dimensional cell, a modified single-cell erase command to perform a modified single-level cell erase on the block is issued.

Abstract: Storage devices include a memory array comprised of a plurality of memory devices arranged in word lines. The word lines are further arranged within memory blocks. When erasing memory blocks, various storage devices may utilize a stripe-erase process that alternates the erasure of word lines within the memory blocks. The stripe-erase process is often carried out in multiple steps. However, an ungraceful shutdown can interrupt the erasing processing between one of these stripe-erase steps. The status of each memory device associated with the aborted erasure needs to be known before operations can continue. Methods and systems described herein properly classify and process memory blocks after an aborted erase command by analyzing both even and odd word lines within each of the memory blocks. By properly categorizing each memory block, overprogramming and other negative effects can be avoided, increasing the overall lifespan of the storage device that utilizes a stripe-erase process.