Abstract: Disclosed herein is a pseudo-random binary sequence (PRBS) generator (200) for performing on-chip testing. It comprises of a plurality of lanes (L1-L4), wherein each lane comprises a latch group (Lg1-Lg4) capable of receiving clock signals, wherein a number of latches in each latch group is based on an output sequence to be generated for performing the on-chip testing. Each latch group is having at least one of a flip-flop and a latch is further connected with a plurality of logic gates in such a manner that an output, generated by the at least one of the flip-flop and the latch of each latch group, is provided as an input to the plurality of logic gates.

Abstract: Disclosed herein is a pseudo-random binary sequence (PRBS) generator (200) for performing on-chip testing. It comprises of a plurality of lanes (L1-L4), wherein each lane comprises a latch group (Lg1-Lg4) capable of receiving clock signals, wherein a number of latches in each latch group is based on an output sequence to be generated for performing the on-chip testing. Each latch group is having at least one of a flip-flop and a latch is further connected with a plurality of logic gates in such a manner that an output, generated by the at least one of the flip-flop and the latch of each latch group, is provided as an input to the plurality of logic gates.

Abstract: Embodiments of the disclosure may generally relate to an analog to digital converter. An example analog to digital converter may include a unit capacitor array, a comparator and a control block. The unit capacitor array may include multiple capacitors coupled to one another via multiple switches under control of the control block. The comparator, having a first input and a second input, may be configured to receive a controlled voltage generated from the unit capacitor array and compare an analog voltage to the controlled voltage. The control block may be configured to selectively open or close the switches, receive a comparison result from the comparator, and generate a digital output based on the comparison result. The control block may be configured to control the switch timing of the unit capacitor array for reset, pre-charge, charge redistribution, and comparison phases, where a passive charge redistribution method may be utilized.

Abstract: Techniques are generally described herein for analog to digital conversion. Some example ADC converters include a unit capacitor array coupled to a reference voltage, where the capacitor array includes multiple capacitors coupled to one another via multiple switches under control of a control block. A comparator, having a first input and a second input, is configured to receive a controlled voltage generated from the unit capacitor array and compare an analog voltage to the controlled voltage. The control block is configured to selectively open or close the switches, receive a comparison result from the comparator, and generate a digital output based On the comparison result. The control block is configured to control the switch timing of the unit capacitor array for reset, pre-charge, charge redistribution, and comparison phases, where a passive charge redistribution method may be utilized.