Patents by Inventor Vinayak K. Shamanna

Vinayak K. Shamanna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9397210
    Abstract: A memory array has first and second memory cells over a semiconductor and an isolation region extending into the semiconductor. The isolation region includes an air gap between charge-storage structures of the first and second memory cells and a thickness of dielectric over the air gap and contained between the first and second memory cells.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: July 19, 2016
    Assignee: Micron Technology, Inc.
    Inventors: James Mathew, Gordon Haller, Ronald A. Weimer, John Hopkins, Vinayak K. Shamanna, Sanjeev Sapra
  • Patent number: 9082714
    Abstract: Embodiments of the present disclosure are directed towards use of an etch process post wordline definition to improve data retention in a flash memory device. In one embodiment, a method includes forming a plurality of wordline structures on a substrate, wherein individual wordline structures of the plurality of wordline structures include a control gate having an electrically conductive material and a cap having an electrically insulative material formed on the control gate, depositing an electrically insulative material to form a liner on a surface of the individual wordline structures, and etching the liner to remove at least a portion of the liner. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: July 14, 2015
    Assignee: Intel Corporation
    Inventors: Randy J. Koval, Max F. Hineman, Ronald A. Weimer, Vinayak K. Shamanna, Thomas M. Graettinger, William R. Kueber, Christopher Larsen, Alex J. Schrinsky
  • Publication number: 20140027832
    Abstract: A memory array has first and second memory cells over a semiconductor and an isolation region extending into the semiconductor. The isolation region includes an air gap between charge-storage structures of the first and second memory cells and a thickness of dielectric over the air gap and contained between the first and second memory cells.
    Type: Application
    Filed: October 2, 2013
    Publication date: January 30, 2014
    Applicant: Micron Technology, Inc.
    Inventors: James Mathew, Gordon Haller, Ronald A. Weimer, John Hopkins, Vinayak K. Shamanna, Sanjeev Sapra
  • Patent number: 8569130
    Abstract: Methods of forming air gaps in memory arrays and memory arrays with air gaps thus formed are disclosed. One such method may include forming an isolation region, having a first dielectric, through a charge-storage structure that is over a semiconductor, the isolation region extending into the semiconductor; forming a second dielectric over the isolation region and charge-storage structure; and forming an air gap in the isolation region so that the air gap passes through the charge-storage structure and so that a thickness of the first dielectric is between the air gap and the second dielectric.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: October 29, 2013
    Assignee: Micron Technology, Inc.
    Inventors: James Mathew, Gordon Haller, Ronald A. Weimer, John Hopkins, Vinayak K. Shamanna, Sanjeev Sapra
  • Publication number: 20130264628
    Abstract: Embodiments of the present disclosure describe techniques and configurations relating to use of an etch process post wordline definition to improve data retention in a flash memory device. In one embodiment, a method includes forming a plurality of wordline structures on a substrate, wherein individual wordline structures of the plurality of wordline structures include a control gate having an electrically conductive material and a cap having an electrically insulative material formed on the control gate, depositing an electrically insulative material to form a liner on a surface of the individual wordline structures, and etching the liner to remove at least a portion of the liner. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 22, 2011
    Publication date: October 10, 2013
    Inventors: Randy J. Koval, Max F. Hineman, Ronald A. Weimer, Vinayak K. Shamanna, Thomas M. Graettinger, William R. Kueber, Christopher Larsen, Alex J. Schrinsky
  • Publication number: 20130026600
    Abstract: Methods of forming air gaps in memory arrays and memory arrays with air gaps thus formed are disclosed. One such method may include forming an isolation region, having a first dielectric, through a charge-storage structure that is over a semiconductor, the isolation region extending into the semiconductor; forming a second dielectric over the isolation region and charge-storage structure; and forming an air gap in the isolation region so that the air gap passes through the charge-storage structure and so that a thickness of the first dielectric is between the air gap and the second dielectric.
    Type: Application
    Filed: July 28, 2011
    Publication date: January 31, 2013
    Inventors: James Matthew, Gordon Haller, Ronald A. Weimer, John Hopkins, Vinayak K. Shamanna, Sanjeev Sapra