Patents by Inventor Vinayak Rastogi
Vinayak Rastogi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10971373Abstract: Methods and systems for cyclic etching of a patterned layer are described. In an embodiment, a method includes receiving a substrate comprising an underlying layer, a mask layer that exposes portions of an intermediate layer that is disposed between the underlying layer and the mask layer. An embodiment may also include forming a first layer on the mask layer and a second layer on the exposed portions of the intermediate layer, the first layer and the second layer being concurrently formed. Additionally, the method may include removing, concurrently, the first layer and the second layer from the substrate. In such embodiments, the method may include alternating between the forming and the removing until portions of the underlying layer are exposed.Type: GrantFiled: June 19, 2019Date of Patent: April 6, 2021Assignee: Tokyo Electron LimitedInventors: Alok Ranjan, Vinayak Rastogi
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Patent number: 10541146Abstract: A method of etching is described. The method includes providing a substrate having a first material containing organic material and a second material that is different from the first material, forming a first chemical mixture by plasma-excitation of a first process gas containing an inert gas, and exposing the first material on the substrate to the first chemical mixture. Thereafter, the method includes forming a second chemical mixture by plasma-excitation of a second process gas containing S and O, and optionally a noble element, and exposing the first material on the substrate to the second plasma-excited process gas to selectively etch the first material relative to the second material.Type: GrantFiled: April 26, 2018Date of Patent: January 21, 2020Assignee: TOKYO ELECTRON LIMITEDInventors: Vinayak Rastogi, Alok Ranjan
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Patent number: 10535531Abstract: A method of etching is described. The method includes providing a substrate having a first material containing organic material and a second material that is different from the first material, forming a first chemical mixture by plasma-excitation of a first process gas containing an inert gas, and exposing the first material on the substrate to the first chemical mixture. Thereafter, the method includes forming a second chemical mixture by plasma-excitation of a second process gas containing C and O, and optionally a noble element, and exposing the first material on the substrate to the second plasma-excited process gas to selectively etch the first material relative to the second material.Type: GrantFiled: April 26, 2018Date of Patent: January 14, 2020Assignee: TOKYO ELECTRON LIMITEDInventors: Vinayak Rastogi, Alok Ranjan
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Publication number: 20190304798Abstract: Methods and systems for cyclic etching of a patterned layer are described. In an embodiment, a method includes receiving a substrate comprising an underlying layer, a mask layer that exposes portions of an intermediate layer that is disposed between the underlying layer and the mask layer. An embodiment may also include forming a first layer on the mask layer and a second layer on the exposed portions of the intermediate layer, the first layer and the second layer being concurrently formed. Additionally, the method may include removing, concurrently, the first layer and the second layer from the substrate. In such embodiments, the method may include alternating between the forming and the removing until portions of the underlying layer are exposed.Type: ApplicationFiled: June 19, 2019Publication date: October 3, 2019Applicant: Tokyo Electron LimitedInventors: Alok Ranjan, Vinayak Rastogi
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Patent number: 10381235Abstract: Embodiments of the invention provide a substrate processing method for selective SiN etching relative to other layers used in semiconductor manufacturing. According to one embodiment, the substrate processing method includes providing in a plasma processing chamber a substrate containing a first material containing silicon nitride and a second material that is different from the first material, forming a plasma-excited process gas containing NF3 and O2, and exposing the substrate to the plasma-excited process gas to selectively etch the first material relative to the second material. According to one embodiment, the second material may be selected from the group consisting of Si, SiO2, and a combination thereof.Type: GrantFiled: May 26, 2017Date of Patent: August 13, 2019Assignee: Tokyo Electron LimitedInventors: Alok Ranjan, Vinayak Rastogi, Sonam D. Sherpa
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Patent number: 10366902Abstract: Methods and systems for cyclic etching of a patterned layer are described. In an embodiment, a method includes receiving a substrate comprising an underlying layer, a mask layer that exposes portions of an intermediate layer that is disposed between the underlying layer and the mask layer. An embodiment may also include forming a first layer on the mask layer and a second layer on the exposed portions of the intermediate layer, the first layer and the second layer being concurrently formed. Additionally, the method may include removing, concurrently, the first layer and the second layer from the substrate. In such embodiments, the method may include alternating between the forming and the removing until portions of the underlying layer are exposed.Type: GrantFiled: February 22, 2017Date of Patent: July 30, 2019Assignee: Tokyo Electron LimitedInventors: Alok Ranjan, Vinayak Rastogi
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Publication number: 20180315615Abstract: A method of etching is described. The method includes providing a substrate having a first material containing organic material and a second material that is different from the first material, forming a first chemical mixture by plasma-excitation of a first process gas containing an inert gas, and exposing the first material on the substrate to the first chemical mixture. Thereafter, the method includes forming a second chemical mixture by plasma-excitation of a second process gas containing S and O, and optionally a noble element, and exposing the first material on the substrate to the second plasma-excited process gas to selectively etch the first material relative to the second material.Type: ApplicationFiled: April 26, 2018Publication date: November 1, 2018Inventors: Vinayak Rastogi, Alok Ranjan
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Publication number: 20180315616Abstract: A method of etching is described. The method includes providing a substrate having a first material containing organic material and a second material that is different from the first material, forming a first chemical mixture by plasma-excitation of a first process gas containing an inert gas, and exposing the first material on the substrate to the first chemical mixture. Thereafter, the method includes forming a second chemical mixture by plasma-excitation of a second process gas containing C and O, and optionally a noble element, and exposing the first material on the substrate to the second plasma-excited process gas to selectively etch the first material relative to the second material.Type: ApplicationFiled: April 26, 2018Publication date: November 1, 2018Inventors: Vinayak Rastogi, Alok Ranjan
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Publication number: 20180294168Abstract: Methods for anisotropic dry etching of titanium-containing films used in semiconductor manufacturing have been disclosed in various embodiments. According to one embodiment, the method includes providing a substrate having a titanium-containing film thereon, and etching the titanium-containing film by a) exposing the substrate to a chlorine-containing gas to form a chlorinated layer on the substrate, b) exposing the substrate to a plasma-excited inert gas to remove the chlorinated layer, and c) repeating the exposing steps at least once.Type: ApplicationFiled: April 10, 2018Publication date: October 11, 2018Inventors: Kandabara N. Tapily, Vinayak Rastogi, Alok Ranjan
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Patent number: 9947597Abstract: The described embodiments include performing a curing process for selective treatment, or hardening, of PS regions in PS-b-PMMA block copolymer DSA films prior to dry etch development of PMMA regions. In various embodiments, the curing chemistry can be Ar/H2, HBr, N2/H2, etc., which has the capability of generating Vacuum Ultraviolet (VUV) photon flux for polymer curing. The curing effect may enhance the etch resistance of PS regions, thereby freezing the bulk defects during plasma PMMA removal. The defects can then be measured by commonly used metrology techniques like CDSEM and quantized.Type: GrantFiled: March 17, 2017Date of Patent: April 17, 2018Assignee: Tokyo Electron LimitedInventors: Vinayak Rastogi, Alok Ranjan
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Publication number: 20170345674Abstract: Embodiments of the invention provide a substrate processing method for selective SiN etching relative to other layers used in semiconductor manufacturing. According to one embodiment, the substrate processing method includes providing in a plasma processing chamber a substrate containing a first material containing silicon nitride and a second material that is different from the first material, forming a plasma-excited process gas containing NF3 and O2, and exposing the substrate to the plasma-excited process gas to selectively etch the first material relative to the second material. According to one embodiment, the second material may be selected from the group consisting of Si, SiO2, and a combination thereof.Type: ApplicationFiled: May 26, 2017Publication date: November 30, 2017Inventors: Alok Ranjan, Vinayak Rastogi, Sonam D. Sherpa
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Publication number: 20170345673Abstract: Embodiments of the invention provide a substrate processing method for selective SiO2 etching relative to other layers used in semiconductor manufacturing. The method includes providing a substrate containing a first layer containing SiO2 and a second layer that is different from the first layer, forming a plasma-excited process gas containing 1) NF3 and NH3, 2) NF3, N2 and H2, or 3) NF3, NH3, N2 and H2, and exposing the substrate to the plasma-excited process gas to selectively etch the first layer relative to the second layer. According to one embodiment, the second layer includes SiN or elemental Si.Type: ApplicationFiled: May 24, 2017Publication date: November 30, 2017Inventors: Alok Ranjan, Akira Koshiishi, Sonam D. Sherpa, Vinayak Rastogi
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Publication number: 20170287790Abstract: The described embodiments include performing a curing process for selective treatment, or hardening, of PS regions in PS-b-PMMA block copolymer DSA films prior to dry etch development of PMMA regions. In various embodiments, the curing chemistry can be Ar/H2, HBr, N2/H2, etc., which has the capability of generating Vacuum Ultraviolet (VUV) photon flux for polymer curing. The curing effect may enhance the etch resistance of PS regions, thereby freezing the bulk defects during plasma PMMA removal. The defects can then be measured by commonly used metrology techniques like CDSEM and quantized.Type: ApplicationFiled: March 17, 2017Publication date: October 5, 2017Inventors: Vinayak Rastogi, Alok Ranjan
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Publication number: 20170243757Abstract: Methods and systems for cyclic etching of a patterned layer are described. In an embodiment, a method includes receiving a substrate comprising an underlying layer, a mask layer that exposes portions of an intermediate layer that is disposed between the underlying layer and the mask layer. An embodiment may also include forming a first layer on the mask layer and a second layer on the exposed portions of the intermediate layer, the first layer and the second layer being concurrently formed. Additionally, the method may include removing, concurrently, the first layer and the second layer from the substrate. In such embodiments, the method may include alternating between the forming and the removing until portions of the underlying layer are exposed.Type: ApplicationFiled: February 22, 2017Publication date: August 24, 2017Inventors: Alok Ranjan, Vinayak Rastogi
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Patent number: 9666447Abstract: A method of etching a layer on a substrate is described. The method includes disposing a substrate having a heterogeneous layer composed of a first material and a second material in a processing space of a plasma processing system, wherein the heterogeneous layer has an initial upper surface exposing the first material and the second material to a plasma environment in the processing space, and performing a modulated plasma etching process to selectively remove the first material at a rate greater than removing the second material. The modulated plasma etching process includes a modulation cycle that preferentially reacts an etchant with the first material during a first phase of the modulation cycle, and differentially adheres a passivant on the second material relative to the first material during a second phase of the modulation cycle.Type: GrantFiled: October 22, 2015Date of Patent: May 30, 2017Assignee: TOKYO ELECTRON LIMITEDInventors: Vinayak Rastogi, Alok Ranjan
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Patent number: 9607843Abstract: A method of patterning a silicon containing ARC (anti-reflective coating) layer underlying a patterned layer is described that includes establishing a flow of a process gas to a plasma processing system, selecting a process condition that increases an etch selectivity of the silicon containing ARC layer relative to the patterned layer, igniting plasma from the process gas using a plasma source in accordance with the process condition, and exposing the substrate to the plasma to extend the feature pattern of the patterned layer into the silicon containing ARC layer. The composition of the process gas and the flow rate(s) of the gaseous constituents in the process gas are selected to adjust the carbon-fluorine content.Type: GrantFiled: June 26, 2015Date of Patent: March 28, 2017Assignee: Tokyo Electron LimitedInventors: Vinayak Rastogi, Alok Ranjan
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Patent number: 9576816Abstract: A method of patterning a silicon containing ARC (anti-reflective coating) layer underlying a patterned layer is described that includes establishing a flow of a process gas to a plasma processing system, selecting a process condition that increases an etch selectivity of the silicon containing ARC layer relative to the patterned layer, igniting plasma from the process gas using a plasma source in accordance with the process condition, and exposing the substrate to the plasma to extend the feature pattern of the patterned layer into the silicon containing ARC layer. The process gas includes a first gaseous molecular constituent composed of C, F and optionally H, a second gaseous molecular constituent composed of C, F, and optionally H, and a third gaseous molecular constituent containing atomic hydrogen, diatomic hydrogen, or a CxHy-containing gas, wherein x and y are real numbers greater than zero.Type: GrantFiled: June 26, 2015Date of Patent: February 21, 2017Assignee: Tokyo Electron LimitedInventors: Vinayak Rastogi, Alok Ranjan
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Patent number: 9576812Abstract: Provided is a method of creating structure profiles on a substrate using faceting and passivation layers. A first plasma etch process performed generating a faceted sidewall and a desired inflection point; a second plasma etch process is performed using an oxygen, nitrogen, or combined oxygen and nitrogen plasma, generating a passivation layer; and a third plasma etch process using operating variables of an etch chemistry on the faceted sidewall and the passivation layer to induce differential etch rates to achieve a breakthrough on near-horizontal surfaces of the structure, wherein the third plasma etch used is configured to produce a target sidewall profile on the substrate down to the underlying stop layer. Selected two or more plasma etch variables are controlled in the performance of the first plasma etch process, the second plasma etch process, and/or the third plasma etch process in order to achieve target sidewall profile objectives.Type: GrantFiled: March 30, 2016Date of Patent: February 21, 2017Assignee: Tokyo Electron LimitedInventors: Elliott Franke, Vinayak Rastogi, Akiteru Ko, Kiyohito Ito
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Patent number: 9530667Abstract: A method of patterning a silicon containing ARC (anti-reflective coating) layer underlying a patterned layer is described that includes establishing a flow of a process gas to a plasma processing system, selecting a process condition that increases an etch selectivity of the silicon containing ARC layer relative to the patterned layer, igniting plasma from the process gas using a plasma source in accordance with the process condition, and exposing the substrate to the plasma to extend the feature pattern of the patterned layer into the silicon containing ARC layer. The process gas includes a first gaseous molecular constituent composed of C, F and optionally H, a second gaseous molecular constituent composed of C, F, and optionally H, and a third gaseous molecular constituent composed of C and an element selected from the group consisting of H and F.Type: GrantFiled: June 26, 2015Date of Patent: December 27, 2016Assignee: Tokyo Electron LimitedInventors: Vinayak Rastogi, Alok Ranjan
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Publication number: 20160293435Abstract: Provided is a method of creating structure profiles on a substrate using faceting and passivation layers. A first plasma etch process performed generating a faceted sidewall and a desired inflection point; a second plasma etch process is performed using an oxygen, nitrogen, or combined oxygen and nitrogen plasma, generating a passivation layer; and a third plasma etch process using operating variables of an etch chemistry on the faceted sidewall and the passivation layer to induce differential etch rates to achieve a breakthrough on near-horizontal surfaces of the structure, wherein the third plasma etch used is configured to produce a target sidewall profile on the substrate down to the underlying stop layer. Selected two or more plasma etch variables are controlled in the performance of the first plasma etch process, the second plasma etch process, and/or the third plasma etch process in order to achieve target sidewall profile objectives.Type: ApplicationFiled: March 30, 2016Publication date: October 6, 2016Inventors: Elliott Franke, Vinayak Rastogi, Akiteru Ko, Kiyohito Ito