Abstract: Simulating a circuit design using a data processing system includes partitioning the circuit design into a top-level design and a sub-design along a boundary defined by one or more stream channels coupling a component of the top-level design with the sub-design. The sub-design is extracted from the circuit design and replaced with a stub having a client socket. A wrapper having a server socket is added to the sub-design. The top-level design and the sub-design are compiled into respective simulation kernels. The circuit design is simulated by executing the respective simulation kernels concurrently. The respective kernels communicate over a socket connection established by the client socket and the server socket. In other aspects, the partitioning results in partitions such that one partition is simulated as software and another partition is implemented in circuitry such that the circuit design may be hardware co-simulated.

Abstract: Verification for a design can include, for a covergroup corresponding to a variable of the design, generating a state coverage data structure specifying a plurality of transition bins. Each transition bin can include a sequence. Each sequence can specify states of the variable to be traversed in order during simulation of the design. Verification can include generating a state sequence table configured to use state values as keys and one or more of the sequences as data for the respective keys, and during simulation of the design, maintaining a sequence list specifying each sequence that is running based on sample values of the variable. Hit counts for the transition bins can be updated during the simulation.