Abstract: Aspects of the present disclosure are presented for an AI solution model processing infrastructure that allows owners of machines that perform AI model training and inference to rent the processing resources of the AI machines as a service to the one or more subscribers on an as-needed basis. This allows a subscriber to dynamically rent the service to run one or more AI models to train or infer in a given place/location to accomplish particular AI goals without owning an AI solution model processing-capable machine at a given location. Rather than going through the hard work, resource utilization and cost of doing setting one's own AI compute processing, the rental service described herein will provide a pay as you need scheme to run one's AI model in a rented environment.

Abstract: Aspects of the present disclosure provide for a novel system and method where users can promote, subscribe, license, train collaboratively, and/or trade AI models in real-time over an AI trusted model network that represents a group of trusted users across platform agnostic ways. The system and methods described herein may effectively provide a marketplace to collaboratively develop and reliably disseminate developed AI models to other users who may have similar needs. The system may include an AI user device server (AI-UDS), an AI trusted model network (AI-TMN), an AI secure marketplace system (AI-SMPS), an AI collaborative training platform (AI-CTP), an AI secure transaction fulfillment system (AI-STFS), and an AI model license subscription management platform (AI-LSMP).

Abstract: Aspects of the present disclosure are presented for an AI system featuring specially designed AI hardware that incorporates security features to provide iron clad trust and security to run AI applications/solution models. Presented herein are various security features for AI processing, including: a trust and integrity verifier of data during operation of an AI solution model; identity and trust establishment between an entity and the AI solution model; secure isolation for a virtual AI multilane system; a real-time attack detection and prevention mechanism; and built in detection mechanisms related to rogue security attack elements insertion during manufacturing. Aspects also include security to implement an AI network interconnecting multiple user devices in an AI environment.

Abstract: Aspects of the present disclosure are presented for a power management system of a multilane AI system architecture. The system may include an orchestrator configured to control power and other operations of a lane. An uber orchestrator manages the overall system, and may know all of the multilane systems within the AI virtual multilane system that need to be active at a given frequency and power envelope for given price, and performance constraints. The orchestrator of each lane knows the compute/logic blocks that need to be active for a given AI app model AI processing chain execution. The orchestrator may be configured to send commands to turn off power to certain components that are not utilized in performing an AI execution sequence, deactivate operation to the lane when its functions are completed, and also modulate the clock frequency of a lane to fit the computation demands while minimizing power usage.

Abstract: An artificial intelligence (AI) system is disclosed. The AI system provides an AI system lane processing chain, at least one AI processing block, a local memory, a hardware sequencer, and a lane composer. Each of the at least one AI processing block, the local memory coupled to the AI system lane processing chain, the hardware sequencer coupled to the AI system lane processing chain, and the lane composer is coupled to the AI system lane processing chain. The AI system lane processing chain is dynamically created by the lane composer.

Abstract: Aspects of the present disclosure are presented for an autonomous adaptive AI self-learning, training and inferencing system and method that would provide extremely cost effective and energy efficient broad based AI solutions/applications that are personalized/customizable. In some embodiments, a proposed component is an intelligent sense neuro memory cell unit (ISN-MCU). The ISN-MCU acts as the basic building block for AI adaptive learning. Each ISN-MCU is capable of receiving input from the surrounding environment and then learning or making an inference about the received data. With enough time or many more ISN-MCUs in combination, the AI system may be capable of learning for what it was programmed for in real time and in a memory and time efficient manner.

Abstract: Aspects of the disclosure are presented for an elegant mechanism to allow for AI training using an AI system that is platform agnostic and eliminates the need for multi processors, e.g., CPU, VMs, OS & GPU based full stack software AI frameworks. The AI system may utilize an asynchronous or file system interface, allowing for a send/drop interface of an input data file to automatically run training or inference of an AI solution model. Existing AI solutions would require multi machine learning, deep learning frameworks, and/or one or more SDKs to run to run on CPU, GPU and accelerator environments. The present disclosures utilize special AI hardware that does not rely on such conventional implementations.

Abstract: An artificial intelligence (AI) system is disclosed. The AI system provides an energy efficient hyper parallel and pipelined temporal and spatial scalable secure AI hardware with minimized external memory access. One or more than one re-configurable AI compute engine blocks may be interconnected via one or more high speed interconnect busses to enable an AI processing chain and data exchange between themselves. A hardware sequencer is disclosed to enable an AI processing chain execution driven by dynamically composed AI processing chains.

Abstract: An exemplary system, method and computer-accessible medium for determining a starting point of a header field(s) in a network packet(s) can be provided, which can include, for example receiving the network(s) packet, determining a header location of the header field(s) in the network packet(s), determining a delimiter location of a delimiter(s) in the network packet(s), and determining the starting point of the header field(s) based on the header and delimiter locations. The header location can be determined using a header finder module. The delimiter location can be determined using a delimiter finder module. The header and delimiter locations can be determined using a plurality of comparators arranged into a plurality of sets.

Abstract: An exemplary system, method and computer-accessible medium for determining a starting point of a header field(s) in a network packet(s) can be provided, which can include, for example receiving the network(s) packet, determining a header location of the header field(s) in the network packet(s), determining a delimiter location of a delimiter(s) in the network packet(s), and determining the starting point of the header field(s) based on the header and delimiter locations. The header location can be determined using a header finder module. The delimiter location can be determined using a delimiter finder module. The header and delimiter locations can be determined using a plurality of comparators arranged into a plurality of sets.

Abstract: A ring oscillator (RO) based Design-For-Trust (DFTr) technique is described. Functional paths of integrated circuit (IC) are included in one or more embedded ROs by (1) selecting a path in the IC, based on path selection criteria, that has one or more unsecured gates, and (2) embedding one or more ROs on the IC until a stop condition is met. An input pattern to activate embedded RO is determined. Further, a golden frequency which is a frequency at which the embedded RO oscillates, and a frequency range of the embedded RO are determined. A Trojan in the IC may be detected by activating the embedded RO (by applying the input pattern), measuring a frequency at which the embedded RO oscillates, and determining whether or not a Trojan is present based on whether or not the measured frequency of the RO is within a predetermined operating frequency range of the RO.

Abstract: A ring oscillator (RO) based Design-For-Trust (DFTr) technique is described. Functional paths of integrated circuit (IC) are included in one or more embedded ROs by (1) selecting a path in the IC, based on path selection criteria, that has one or more unsecured gates, and (2) embedding one or more ROs on the IC until a stop condition is met. An input pattern to activate embedded RO is determined. Further, a golden frequency which is a frequency at which the embedded RO oscillates, and a frequency range of the embedded RO are determined. A Trojan in the IC may be detected by activating the embedded RO (by applying the input pattern), measuring a frequency at which the embedded RO oscillates, and determining whether or not a Trojan is present based on whether or not the measured frequency of the RO is within a predetermined operating frequency range of the RO.