Patents by Inventor Vinaykumar HADAGALI

Vinaykumar HADAGALI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of contact patterning of thin film transistors for embedded DRAM using a multi-layer hardmask
    Patent number: 11563107
    Abstract: An integrated circuit structure comprises one or more backend-of-line (BEOL) interconnects formed over a first ILD layer. An etch stop layer is over the one or more BEOL interconnects, the etch stop layer having a plurality of vias that are in contact with the one or more BEOL interconnects. An array of BEOL thin-film-transistors (TFTs) is over the etch stop layer, wherein adjacent ones of the BEOL TFTs are separated by isolation trench regions. The TFTs are aligned with at least one of the plurality of vias to connect to the one or more BEOL interconnects, wherein each of the BEOL TFTs comprise a bottom gate electrode, a gate dielectric layer over the bottom gate electrode, and an oxide-based semiconductor channel layer over the bottom gate electrode having source and drain regions therein. Contacts are formed over the source and drain regions of each of BEOL TFTs, wherein the contacts have a critical dimension of 35 nm or less, and wherein the BEOL TFTs have an absence of diluted hydro-fluoride (DHF).
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: January 24, 2023
    Assignee: Intel Corporation
    Inventors: Chieh-Jen Ku, Bernhard Sell, Pei-Hua Wang, Nikhil Mehta, Shu Zhou, Jared Stoeger, Allen B. Gardiner, Akash Garg, Shem Ogadhoh, Vinaykumar Hadagali, Travis W. Lajoie
  • METHOD OF CONTACT PATTERNING OF THIN FILM TRANSISTORS FOR EMBEDDED DRAM USING A MULTI-LAYER HARDMASK
    Publication number: 20200303520
    Abstract: An integrated circuit structure comprises one or more backend-of-line (BEOL) interconnects formed over a first ILD layer. An etch stop layer is over the one or more BEOL interconnects, the etch stop layer having a plurality of vias that are in contact with the one or more BEOL interconnects. An array of BEOL thin-film-transistors (TFTs) is over the etch stop layer, wherein adjacent ones of the BEOL TFTs are separated by isolation trench regions. The TFTs are aligned with at least one of the plurality of vias to connect to the one or more BEOL interconnects, wherein each of the BEOL TFTs comprise a bottom gate electrode, a gate dielectric layer over the bottom gate electrode, and an oxide-based semiconductor channel layer over the bottom gate electrode having source and drain regions therein. Contacts are formed over the source and drain regions of each of BEOL TFTs, wherein the contacts have a critical dimension of 35 nm or less, and wherein the BEOL TFTs have an absence of diluted hydro-fluoride (DHF).
    Type: Application
    Filed: March 22, 2019
    Publication date: September 24, 2020
    Inventors: Chieh-Jen KU, Bernhard SELL, Pei-Hua WANG, Nikhil MEHTA, Shu ZHOU, Jared STOEGER, Allen B. GARDINER, Akash GARG, Shem OGADHOH, Vinaykumar HADAGALI, Travis W. LAJOIE