Abstract: Clock generating apparatus for a computer system has selective pulse delay and pulse width control. Selection of pulse delay and pulse width is accomplished by loading registers with predetermined data patterns. The registers can be loaded under program control or by data entry units, such as a keyboard, switches, etc. The registers are located in coarse and fine pulse delay and pulse width adjustment units. These units have the same physical structure, but are functionally definable by a settable control element. A dither delay element is included in these coarse and fine adjustment units, and it is selectable to provide a small increment of delay. The coarse pulse delay and pulse width adjustment units also include pulse mode control circuitry to control operation in either normal oscillator mode or in single cycle mode.

Abstract: A negative shunt feedback CMOS amplifier is disclosed for connection to the output nodes of MOS interchip digital signal receiver differential amplifiers which have highly capacitive output nodes in order to bypass the large capacitance to thereby extract a high speed current signal. A first embodiment of the invention uses a resistor as the shunt feedback and a second embodiment of the invention, to which this application is directed to, uses parallel N-channel and P-channel FETs to form the shunt feedback impedance.