Abstract: A voltage regulator comprises first and second amplifier stages, a common-source output stage and a feedback path. The output stage drives a capacitive load with a regulated voltage responsive to a signal applied to the output stage. The capacitive load sets the dominant pole of the voltage regulator. The first amplifier stage amplifies the difference between the regulated voltage and a reference voltage. The second amplifier stage drives the output stage with a signal corresponding to the difference between the regulated voltage and the reference voltage. The feedback path couples an output node of the second amplifier stage to an input node of the second amplifier stage for reducing the output resistance of the second amplifier stage to shift a non-dominant pole of the voltage regulator set by the second amplifier stage.

Abstract: A voltage regulator comprises first and second amplifier stages, a common-source output stage and a feedback path. The output stage drives a capacitive load with a regulated voltage responsive to a signal applied to the output stage. The capacitive load sets the dominant pole of the voltage regulator. The first amplifier stage amplifies the difference between the regulated voltage and a reference voltage. The second amplifier stage drives the output stage with a signal corresponding to the difference between the regulated voltage and the reference voltage. The feedback path couples an output node of the second amplifier stage to an input node of the second amplifier stage for reducing the output resistance of the second amplifier stage to shift a non-dominant pole of the voltage regulator set by the second amplifier stage.

Abstract: Trim codes are determined for semiconductor devices under test (DUTs), wherein the trim codes correspond to voltage or current reference value adjustments that cause the DUTs to generate desired voltage or current reference values. The technique involves supplying respective trim codes simultaneously to the DUTs to cause them to generate trimmed analog voltage or current references, simultaneously feeding a test analog voltage or current reference having a preselected reference value to the DUTs, and for each DUT, comparing the value of the test analog reference to the values of the trimmed analog references to ascertain the crossing of the value of the test analog reference by the values of the trimmed references, whereby for each DUT the trim code corresponding to the value of the trimmed analog voltage or current reference immediately above or below the crossing is established as the preferred trim code to be used for that DUT.

Abstract: Trim codes are determined for semiconductor devices under test (DUTs), wherein the trim codes correspond to voltage or current reference value adjustments that cause the DUTs to generate desired voltage or current reference values. The technique involves supplying respective trim codes simultaneously to the DUTs to cause them to generate trimmed analog voltage or current references, simultaneously feeding a test analog voltage or current reference having a preselected reference value to the DUTs, and for each DUT, comparing the value of the test analog reference to the values of the trimmed analog references to ascertain the crossing of the value of the test analog reference by the values of the trimmed references, whereby for each DUT the trim code corresponding to the value of the trimmed analog voltage or current reference immediately above or below the crossing is established as the preferred trim code to be used for that DUT.

Abstract: Disclosed is an electrostatic discharge device, typically referred to as a power clamping circuit, for minimizing the effects of an initial ESD event as well as providing protection against subsequent ESD events. The power clamp is left fully turned on during and after an ESD event. Subsequent ESD events are those ESD events occurring shortly after an initial ESD event. By using a blocking device such as a diode, the power clamping circuit is maintained in a strong “on” state that fully discharges the initial ESD event and allows for a more rapid response to subsequent ESD events.