Abstract: Series of first ramps and second ramps are generated. A circuit delivers a first signal representative of the comparison of each first ramp with a set point and delivers a second signal representative of the comparison of each second ramp with the set point. Based on the first and second signals: a first ramp is stopped and a second ramp is started when the first ramp reaches the set point, and a second ramp is stopped and a first ramp is started when the second ramp reaches the set point. The value of the set point is modulated in response a maximum value of the first/second last ramp compared with the set point.

Abstract: The present disclosure relates to a voltage converter and method for pulse frequency modulation-type operation during a start-up phase.

Abstract: In an embodiment, a switching power supply includes: an output stage; a clock generator configured to generate a first clock signal; and a control circuit configured to control the output stage based on the first clock signal, wherein the switching power supply is configured to have a first operating mode synchronized by the first clock signal, and a second operating mode that is asynchronous, wherein the clock generator is configured to maintain the first clock signal at a constant value during the second operating mode.

Abstract: A calibration method of a temperature sensor is provided. The temperature sensor having a current source and a ring oscillator generating a square pulse signal with a temperature-dependent square pulse frequency. The acquisition of a first square pulse frequency measurement at a first temperature from the square pulse signal forms a first measurement point. A second square pulse frequency measurement at a second temperature from the second square pulse signal forms a second measurement point. The determination of the relation data being representative of an affine relation between square pulse frequency measurements and temperatures. The affine relation being defined by a used proportionality coefficient modified with respect to a measured proportionality coefficient of a measured affine relation linking the first measurement point and the second measurement point.

Abstract: Series of first ramps and second ramps are generated. A circuit delivers a first signal representative of the comparison of each first ramp with a set point and delivers a second signal representative of the comparison of each second ramp with the set point. Based on the first and second signals: a first ramp is stopped and a second ramp is started when the first ramp reaches the set point, and a second ramp is stopped and a first ramp is started when the second ramp reaches the set point. The value of the set point is modulated in response a maximum value of the first/second last ramp compared with the set point.

Abstract: An operational amplifier integrated circuit includes a differential pair of transistors having a first input, a second input. A bias current generator applies a bias current to an output of the differential pair of transistors. A control loop generates a control voltage arising from a difference in potentials between the first input and the second input. An additional current that is added to the bias current is generated in response to the control voltage.

Abstract: An integrated circuit includes at least one differential pair of transistors, a bias current generator that is configured to generate a bias current on a bias node that is coupled to a source terminal of each transistor of said differential pair by a respective resistive element. A compensation current generator is configured to generate a compensation current in one of the two resistive elements so as to compensate for a difference between actual values of the threshold voltages of the transistors of said differential pair.

Abstract: An integrated circuit includes at least one differential pair of transistors, a bias current generator that is configured to generate a bias current on a bias node that is coupled to a source terminal of each transistor of said differential pair by a respective resistive element. A compensation current generator is configured to generate a compensation current in one of the two resistive elements so as to compensate for a difference between actual values of the threshold voltages of the transistors of said differential pair.

Abstract: A method for controlling operation of a comparator that includes an amplifier that is connected at an input of the comparator includes neutralizing any change of state of a signal output by the comparator starting from each moment in time at which the change of state of the output signal occurs and lasting for a duration of propagation to compensate for a duration of propagation of signals within the amplifier.

Abstract: A comparator includes a folded cascode stage having positive and negative outputs. The folded cascode stage includes: a common-mode voltage regulation circuit that includes resistive elements that are respectively situated between each of the outputs and a common-mode node. A compensation circuit is configured to regulate a difference between the voltages on the outputs, and is configured to generate a constant and continuous compensation current in the two resistive elements. A hysteresis circuit is configured to offset voltages on the outputs, and to generate a hysteresis current in the two resistive elements.

Abstract: A comparator includes a folded cascode stage having positive and negative outputs. The folded cascode stage includes: a common-mode voltage regulation circuit that includes resistive elements that are respectively situated between each of the outputs and a common-mode node. A compensation circuit is configured to regulate a difference between the voltages on the outputs, and is configured to generate a constant and continuous compensation current in the two resistive elements. A hysteresis circuit is configured to offset voltages on the outputs, and to generate a hysteresis current in the two resistive elements.

Abstract: An operational amplifier integrated circuit includes a differential pair of transistors having a first input, a second input. A bias current generator applies a bias current to an output of the differential pair of transistors. A control loop generates a control voltage arising from a difference in potentials between the first input and the second input. An additional current that is added to the bias current is generated in response to the control voltage.

Abstract: A method for controlling operation of a comparator that includes an amplifier that is connected at an input of the comparator includes neutralizing any change of state of a signal output by the comparator starting from each moment in time at which the change of state of the output signal occurs and lasting for a duration of propagation to compensate for a duration of propagation of signals within the amplifier.

Abstract: A comparison circuit includes an input interface configured to receive input signals and an output interface configured to deliver an output signal. A comparator is coupled between the input interface and the output interface. An amplifier is coupled between the input interface and the comparator. A neutralization circuit is configured to neutralize any change of state of the output signal starting from each moment in time at which the change of state of the output signal occurs and lasting for a second duration of propagation that compensates for a duration of propagation of signals within the amplifier.

Abstract: A comparison circuit includes an input interface configured to receive input signals and an output interface configured to deliver an output signal. A comparator is coupled between the input interface and the output interface. An amplifier is coupled between the input interface and the comparator. A neutralization circuit is configured to neutralize any change of state of the output signal starting from each moment in time at which the change of state of the output signal occurs and lasting for a second duration of propagation that compensates for a duration of propagation of signals within the amplifier.

Abstract: There is disclosed a driver circuit for a power amplifier of class D type having a segmented architecture with at least one current branch which can be powered down in a low power mode of operation of the circuit. The branch comprising a switch with a cascode MOS transistor, the circuit further comprises a bias circuitry adapted for dynamically generating a dynamic bias control signal so as to cause the cascode MOS transistor of the switch to be ‘Off’ in the low power mode.

Abstract: There is disclosed a driver circuit for a power amplifier of class D type having a segmented architecture with at least one current branch which can be powered down in a low power mode of operation of the circuit. The branch comprising a switch with a cascode MOS transistor, the circuit further comprises a bias circuitry adapted for dynamically generating a dynamic bias control signal so as to cause the cascode MOS transistor of the switch to be ‘Off’ in the low power mode.