Patents by Inventor Vincent Chalendard

Vincent Chalendard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Testing of asynchronous reset logic
    Patent number: 11301607
    Abstract: Testing of integrated circuitry, wherein the integrated circuitry includes a flip-flop with an asynchronous input, so that during performance of asynchronous scan patterns, glitches are avoided. Combinatorial logic circuitry delivers a local reset signal to the asynchronous input independent of an assertion of an asynchronous global reset signal. A synchronous scan test is performed of delivery of the local reset signal from the combinatorial logic circuitry while masking delivery of any reset signal to the asynchronous input of the flip-flop. An asynchronous scan test is performed of an asynchronous reset of the flip-flop with the asynchronous global reset signal while masking delivery of the local reset signal to the asynchronous input of the flip-flop.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: April 12, 2022
    Assignee: NXP B.V.
    Inventors: Tom Waayers, Johan Corneel Meirlevede, Paul-Henri Pugliesi-Conti, Vincent Chalendard, Michael Rodat
  • TESTING OF ASYNCHRONOUS RESET LOGIC
    Publication number: 20210109153
    Abstract: Testing of integrated circuitry, wherein the integrated circuitry includes a flip-flop with an asynchronous input, so that during performance of asynchronous scan patterns, glitches are avoided. Combinatorial logic circuitry delivers a local reset signal to the asynchronous input independent of an assertion of an asynchronous global reset signal. A synchronous scan test is performed of delivery of the local reset signal from the combinatorial logic circuitry while masking delivery of any reset signal to the asynchronous input of the flip-flop. An asynchronous scan test is performed of an asynchronous reset of the flip-flop with the asynchronous global reset signal while masking delivery of the local reset signal to the asynchronous input of the flip-flop.
    Type: Application
    Filed: December 18, 2019
    Publication date: April 15, 2021
    Applicant: NXP B.V.
    Inventors: Tom Waayers, Johan Corneel Meirlevede, Paul-Henri Pugliesi-Conti, Vincent Chalendard, Michael Rodat
  • Security measures for preventing attacks that use test mechanisms
    Patent number: 7809934
    Abstract: A system comprising processing logic adapted to determine a type of boot performed by the system and a storage coupled to the processing logic. The processing logic is configured to erase or invalidate a predetermined portion of the storage, and to activate or deactivate an interface by which the system is accessed, if the type of boot comprises a functional boot.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: October 5, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory R. Conti, Pascal Cussonneau, Benoit Drevet, Vincent Chalendard
  • SECURITY MEASURES FOR PREVENTING ATTACKS THAT USE TEST MECHANISMS
    Publication number: 20080091930
    Abstract: A system comprising processing logic adapted to determine a type of boot performed by the system and a storage coupled to the processing logic. The processing logic is configured to erase or invalidate a predetermined portion of the storage, and to activate or deactivate an interface by which the system is accessed, if the type of boot comprises a functional boot.
    Type: Application
    Filed: April 27, 2007
    Publication date: April 17, 2008
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gregory R. Conti, Pascal Cussonneau, Benoit Drevet, Vincent Chalendard