Abstract: A system for reducing system latency, MIPS requirements, and power consumption in a wireless communications system includes part of an upper layer stack processing being performed on a controller to relieve a host processor of some data intensive operations. After the initial connection establishment phase in which the controller may retrieve certain information required for data transmission and stores the same locally, the data source may provide data to the controller, such as, without routing the data through the host. The host may be relieved of the data processing that needs to be done while the data is being transferred.

Abstract: A device has a radio transmitter for a first radio link such as a Bluetooth link, having a coexistence controller arranged to communicate with a co-located other radio transmitter for another radio link, to enable both radio links to use potentially conflicting transmission frequencies. A link monitor monitors the first radio link, according to an output from the coexistence controller. By making the link monitor dependent on the coexistence controller, it can distinguish between transmission losses caused by the coexistence interface, and those caused by other effects, to reduce the risk of a data rate controller unnecessarily reducing a transmission rate if transmission losses caused by the coexistence control are misinterpreted as a drop in link quality.

Abstract: A code patching device is provided for use with a processor having a read-only memory which stores instruction code and a further memory for storing patch code. A plurality of patch address registers each store an address, in the read-only memory, at which a patch is to be performed. A comparator compares the address of the read-only memory that is being accessed by the processor with the addresses stored in the registers. A control unit selects between code from the read-only memory or patch code from the further memory depending on the comparison. The code patching device can replace, on-the-fly, erroneous lines of code from the read-only memory by corrected ones. During an initialization process the patch code is loaded into the further memory and the registers are loaded with the addresses which require patching.

Abstract: The present invention discloses a system and a methodology for enhancing performance during wireless communications by reducing system latency, MIPS requirements and power consumption. The present invention discloses a system and method of wireless data communication in which part of upper layer stack processing is performed on a controller to relieve a host processor of some data intensive operations. After the initial connection establishment phase in which the controller retrieves certain information required for data transmission and stores the same locally, the data source provides data directly to the controller without routing the data through the host. The host is relieved of the data processing that needs to be done while the data is being transferred. Hence, the overall latency of the system is improved because of the optimal routing of data traffic.

Abstract: A device has a radio transmitter for a first radio link such as a Bluetooth link, having a coexistence controller arranged to communicate with a co-located other radio transmitter for another radio link, to enable both radio links to use potentially conflicting transmission frequencies. A link monitor monitors the first radio link, according to an output from the coexistence controller. By making the link monitor dependent on the coexistence controller, it can distinguish between transmission losses caused by the coexistence interface, and those caused by other effects, to reduce the risk of a data rate controller unnecessarily reducing a transmission rate if transmission losses caused by the coexistence control are misinterpreted as a drop in link quality.

Abstract: A code patching device is provided for use with a processor having a read-only memory which stores instruction code and a further memory for storing patch code. A plurality of patch address registers each store an address, in the read-only memory, at which a patch is to be performed. A comparator compares the address of the read-only memory that is being accessed by the processor with the addresses stored in the registers. A control unit selects between code from the read-only memory or patch code from the further memory depending on the comparison. The code patching device can replace, on-the-fly, erroneous lines of code from the read-only memory by corrected ones. During an initialization process the patch code is loaded into the further memory and the registers are loaded with the addresses which require patching.