Patents by Inventor Vincent Chun Fai LAU

Vincent Chun Fai LAU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Logic cell including deep via contact and wiring layers located at different levels
    Patent number: 10707163
    Abstract: A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend in a first direction, one first line of the first lines connected to a first conductive area selected from the plurality of conductive areas through a via contact; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; and a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: July 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Vincent Chun Fai Lau, Jung-ho Do, Byung-sung Kim, Chul-hong Park
  • LOGIC CELL, SEMICONDUCTOR DEVICE INCLUDING LOGIC CELL, AND METHOD OF MANUFACTURING THE LOGIC CELL AND SEMICONDUCTOR DEVICE
    Publication number: 20190109088
    Abstract: A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend in a first direction, one first line of the first lines connected to a first conductive area selected from the plurality of conductive areas through a via contact; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; and a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line.
    Type: Application
    Filed: November 27, 2018
    Publication date: April 11, 2019
    Inventors: Vincent Chun Fai LAU, Jung-ho DO, Byung-sung KIM, Chul-hong PARK
  • Logic cell including single layer via contact and deep via contact
    Patent number: 10177087
    Abstract: A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend in a first direction, one first line of the first lines connected to a first conductive area selected from the plurality of conductive areas through a via contact; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; and a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: January 8, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Vincent Chun Fai Lau, Jung-ho Do, Byung-sung Kim, Chul-hong Park
  • LOGIC CELL, SEMICONDUCTOR DEVICE INCLUDING LOGIC CELL, AND METHOD OF MANUFACTURING THE LOGIC CELL AND SEMICONDUCTOR DEVICE
    Publication number: 20170221818
    Abstract: A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend in a first direction, one first line of the first lines connected to a first conductive area selected from the plurality of conductive areas through a via contact; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; and a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line.
    Type: Application
    Filed: April 21, 2017
    Publication date: August 3, 2017
    Inventors: Vincent Chun Fai LAU, Jung-ho DO, Byung-sung KIM, Chul-hong PARK
  • Logic cell, semiconductor device including logic cell, and method of manufacturing the logic cell and semiconductor device
    Patent number: 9653394
    Abstract: A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend in a first direction, one first line of the first lines connected to a first conductive area selected from the plurality of conductive areas through a via contact; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; and a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: May 16, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Vincent Chun Fai Lau, Jung-ho Do, Byung-sung Kim, Chul-hong Park
  • LOGIC CELL, SEMICONDUCTOR DEVICE INCLUDING LOGIC CELL, AND METHOD OF MANUFACTURING THE LOGIC CELL AND SEMICONDUCTOR DEVICE
    Publication number: 20150357282
    Abstract: A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend in a first direction, one first line of the first lines connected to a first conductive area selected from the plurality of conductive areas through a via contact; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; and a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line.
    Type: Application
    Filed: February 11, 2015
    Publication date: December 10, 2015
    Inventors: Vincent Chun Fai LAU, Jung-ho DO, Byung-sung KIM, Chul-hong PARK