Abstract: An example system-on-chip (SoC) device for a communication system includes a peripheral component interconnect express (PCIe) interface configured to receive data from a backhaul field programmable gate array (FPGA) of the communication system, and a producer port linked with a consumer port through direct memory access (DMA). Data received by the PCIe interface is assigned to the producer port. The device includes dual hardware media access controls (MACs) configured to consume the data assigned to the producer port, and at least one processor configured to supply the data to a wireless interface for transmission to another wireless communication device of the communication system at a frequency of at least sixty Gigahertz.

Abstract: A communication system includes a first communication cable coupled with a first peer node of a data network, a first wireless host device including a first wireless interface and a second wireless interface, a first adapter coupled between the first wireless host device and an end point of the first communication cable, a second communication cable coupled with a second peer node of the data network, and a second wireless host device including a third wireless interface and a fourth wireless interface. The third wireless interface is configured to communicate with the first wireless interface via a first wireless communication channel, and the fourth wireless interface is configured to communicate with the second wireless interface via a second wireless communication channel. A second adapter is coupled between the second wireless host device and the second communication cable.

Abstract: An example system-on-chip (SoC) device for a communication system includes a peripheral component interconnect express (PCIe) interface configured to receive data from a backhaul field programmable gate array (FPGA) of the communication system, and a producer port linked with a consumer port through direct memory access (DMA). Data received by the PCIe interface is assigned to the producer port. The device includes dual hardware media access controls (MACs) configured to consume the data assigned to the producer port, and at least one processor configured to supply the data to a wireless interface for transmission to another wireless communication device of the communication system at a frequency of at least sixty Gigahertz.

Abstract: A communication system includes a first communication cable coupled with a first peer node of a data network, a first wireless host device including a first wireless interface and a second wireless interface, a first adapter coupled between the first wireless host device and an end point of the first communication cable, a second communication cable coupled with a second peer node of the data network, and a second wireless host device including a third wireless interface and a fourth wireless interface. The third wireless interface is configured to communicate with the first wireless interface via a first wireless communication channel, and the fourth wireless interface is configured to communicate with the second wireless interface via a second wireless communication channel. A second adapter is coupled between the second wireless host device and the second communication cable.

Abstract: An example system-on-chip (SoC) device for a communication system includes a peripheral component interconnect express (PCIe) interface configured to receive data from a backhaul field programmable gate array (FPGA) of the communication system, and a producer port linked with a consumer port through direct memory access (DMA). Data received by the PCIe interface is assigned to the producer port. The device includes dual hardware media access controls (MACs) configured to consume the data assigned to the producer port, and at least one processor configured to supply the data to a wireless interface for transmission to another wireless communication device of the communication system at a frequency of at least sixty Gigahertz.

Abstract: A communication system includes a first communication cable coupled with a first peer node of a data network, a first wireless host device including a first wireless interface and a second wireless interface, a first adapter coupled between the first wireless host device and an end point of the first communication cable, a second communication cable coupled with a second peer node of the data network, and a second wireless host device including a third wireless interface and a fourth wireless interface. The third wireless interface is configured to communicate with the first wireless interface via a first wireless communication channel, and the fourth wireless interface is configured to communicate with the second wireless interface via a second wireless communication channel. A second adapter is coupled between the second wireless host device and the second communication cable.

Abstract: A communication system includes a first communication cable coupled with a first peer node of a data network, a first wireless host device including a first wireless interface and a second wireless interface, a first adapter coupled between the first wireless host device and an end point of the first communication cable, a second communication cable coupled with a second peer node of the data network, and a second wireless host device including a third wireless interface and a fourth wireless interface. The third wireless interface is configured to communicate with the first wireless interface via a first wireless communication channel, and the fourth wireless interface is configured to communicate with the second wireless interface via a second wireless communication channel. A second adapter is coupled between the second wireless host device and the second communication cable.

Abstract: In one embodiment, the present invention includes a method for obtaining a physical layout for an integrated circuit (IC) design of a substrate having at least one of an n-well and a deep n-well; and extracting a layout netlist for the IC design from the physical layout by identifying the substrate as a single region. In such manner, short circuits isolated by the n-well or the deep n-well can be detected.

Abstract: In one embodiment, the present invention includes a method for obtaining a physical layout for an integrated circuit (IC) design of a substrate having at least one of an n-well and a deep n-well; and extracting a layout netlist for the IC design from the physical layout by identifying the substrate as a single region. In such manner, short circuits isolated by the n-well or the deep n-well can be detected.