Abstract: Methods and apparatus for bonding chiplets to substrates are provided herein. In some embodiments, a multi-chamber processing tool for processing substrates, includes: a first equipment front end module (EFEM) having one or more loadports for receiving one or more types of substrates, a second EFEM having one or more loadports; and a plurality of atmospheric modular mainframes (AMMs) coupled to each other and having a first AMM coupled to the first EFEM and a last AMM coupled to the second EFEM, wherein each of the plurality of AMMs include a transfer chamber and one or more process chambers coupled to the transfer chamber, wherein the transfer chamber includes a buffer, and wherein the transfer chamber includes a transfer robot, the one or more process chambers, and a buffer disposed in an adjacent AMM of the plurality of AMMs.

Abstract: Methods and apparatus bonding chiplets to substrates are provided herein. In some embodiments, a multi-chamber processing tool for processing a substrate includes: an equipment front end module (EFEM) having one or more loadports for receiving one or more types of substrates; and a plurality of automation modules coupled to each other and having a first automation module coupled to the EFEM, wherein each of the plurality of automation modules include a transfer chamber and one or more process chambers coupled to the transfer chamber, wherein the transfer chamber includes a buffer configured to hold a plurality of the one or more types of substrates, and wherein the transfer chamber includes a transfer robot configured to transfer the one or more types of substrates between the buffer, the one or more process chambers, and a buffer disposed in an adjacent automation module of the plurality of automation modules.

Abstract: The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor package. In one embodiment, a glass or silicon substrate is structured by micro-blasting or laser ablation to form structures for formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor package with embedded dies therein.

Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

Abstract: The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.

Abstract: Methods for bonding semiconductor surfaces leverage hybrid bonding processes to enable heterogeneous integration architectures. In some embodiments, the methods may comprise forming a semiconductor structure on a silicon-based substrate with a first set of exposed conductive connections on a top surface of the semiconductor structure. The first set of exposed conductive connections having a pitch of less than approximately 10 microns. Forming an advanced rectangular substrate panel with a second set of exposed conductive connections. The second set of exposed conductive connections having a pitch of less than approximately 10 microns. Bonding a top surface of the semiconductor structure to a top surface of the advanced rectangular substrate panel using a hybrid bonding process to bond the semiconductor structure to the advanced rectangular substrate panel.

Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

Abstract: Methods and apparatus for electroplating a substrate incorporate aspects of digital lithography and feedback from electroplating processes to improve characteristics of plating material based on die patterns. In some embodiments, a method of electroplating a substrate may include receiving a die design, forming a first lithographic pattern for a first substrate based on the die design, using a digital lithography process to pattern the first substrate with the first lithographic pattern, using an electroplating process to deposit material on the first substrate, using a metrology process to determine at least one parameter of the deposited material on the first substrate, and forming a second lithographic pattern from the first lithographic pattern for a second substrate based, at least in part, on the at least one parameter received directly from the metrology process on the first substrate by the digital lithographic process for the second substrate.

Abstract: The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.

Abstract: The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor package. In one embodiment, a glass or silicon substrate is structured by micro-blasting or laser ablation to form structures for formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor package with embedded dies therein.

Abstract: The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor package. In one embodiment, a glass or silicon substrate is structured by micro-blasting or laser ablation to form structures for formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor package with embedded dies therein.

Abstract: The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.

Abstract: Methods and apparatus for bonding chiplets to substrates are provided herein. In some embodiments, a multi-chamber processing tool for processing substrates, includes: a first equipment front end module (EFEM) having one or more loadports for receiving one or more types of substrates, a second EFEM having one or more loadports; and a plurality of atmospheric modular mainframes (AMMs) coupled to each other and having a first AMM coupled to the first EFEM and a last AMM coupled to the second EFEM, wherein each of the plurality of AMMs include a transfer chamber and one or more process chambers coupled to the transfer chamber, wherein the transfer chamber includes a buffer, and wherein the transfer chamber includes a transfer robot, the one or more process chambers, and a buffer disposed in an adjacent AMM of the plurality of AMMs.

Abstract: Methods and apparatus bonding chiplets to substrates are provided herein. In some embodiments, a multi-chamber processing tool for processing a substrate includes: an equipment front end module (EFEM) having one or more loadports for receiving one or more types of substrates; and a plurality of automation modules coupled to each other and having a first automation module coupled to the EFEM, wherein each of the plurality of automation modules include a transfer chamber and one or more process chambers coupled to the transfer chamber, wherein the transfer chamber includes a buffer configured to hold a plurality of the one or more types of substrates, and wherein the transfer chamber includes a transfer robot configured to transfer the one or more types of substrates between the buffer, the one or more process chambers, and a buffer disposed in an adjacent automation module of the plurality of automation modules.

Abstract: The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.

Abstract: A method and apparatus for forming a plurality of vias in panels for advanced packaging applications is disclosed, according to one embodiment. A redistribution layer is deposited on a substrate layer. The redistribution layer may be deposited using a spin coating process, a spray coating process, a drop coating process, or lamination. The redistribution layer is then micro-imprinted using a stamp inside a chamber. The redistribution layer and the stamp are then baked inside the chamber. The stamp is removed from the redistribution layer to form a plurality of vias in the redistribution layer. Excess residue built-up on the redistribution layer may be removed using a descumming process. A residual thickness layer disposed between the bottom of each of the plurality of vias and the top of the substrate layer may have thickness of less than about 1 ?m.

Abstract: A method for producing an electrical component is disclosed using a molybdenum adhesion layer, connecting a polyimide substrate to a copper seed layer and copper plated attachment.

Abstract: A method and apparatus for forming a plurality of vias in panels for advanced packaging applications is disclosed, according to one embodiment. A redistribution layer is deposited on a substrate layer. The redistribution layer may be deposited using a spin coating process, a spray coating process, a drop coating process, or lamination. The redistribution layer is then micro-imprinted using a stamp inside a chamber. The redistribution layer and the stamp are then baked inside the chamber. The stamp is removed from the redistribution layer to form a plurality of vias in the redistribution layer. Excess residue built-up on the redistribution layer may be removed using a descumming process. A residual thickness layer disposed between the bottom of each of the plurality of vias and the top of the substrate layer may have thickness of less than about 1 ?m.

Abstract: The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.

Abstract: The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor package. In one embodiment, a glass or silicon substrate is structured by micro-blasting or laser ablation to form structures for formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor package with embedded dies therein.