Abstract: A method for controlling expedite cycles having the steps of determining the number of clock cycles devoted to expedite data transfer requests made to a component during a predetermined monitoring window and guaranteeing a minimum number of clock cycles processing non-expedite requests during the monitoring window.

Abstract: A method for controlling device temperature. The method involves determining access rate to a component, comparing the access rate with a predetermined threshold modified by a weighted value and controlling the temperature of the component through corrective action.

Abstract: A computer system is provided. The computer system includes a host processor (HP), a system memory (SM), and an input/output (I/O) master device to perform a read of a continuous stream of data to the SM. The computer system also includes a bridge coupled to the HP, SM, and I/O master device. The bridge reads ahead to the SM when the I/O master device reads a continuous stream of data from the SM. The bridge aborts read ahead accesses to the SM, prior to an access commit point to the SM, responsive to disengagement of the I/O master device.

Abstract: A method for preventing access to a system management random access memory (SMRAM) space is disclosed. The method intercepts access to an accelerated graphics port (AGP) aperture memory space and re-directs the access to non-SMRAM space if the access is directed to the SMRAM space.

Abstract: A method for controlling core logic temperature. The core logic having a memory controller and memory components coupled to system memory. The method having the step of determining access rate to the system memory through the core logic and controlling the temperature of the core logic by adjusting the access rate.

Abstract: A method for graphics device read and processor write coherency receives a write request from a processor to write data to a storage element for a component to read and flushes the data to the storage element prior to the component reading the address associated with the data in the storage element.

Abstract: A method of transmitting a signal from a first clock domain to a second clock domain commences with the generation of first and second clock signals. The first and second clock signals are substantially synchronous and have respective frequencies that are non-integer multiples. A first signal, which is generated in the first clock domain responsive to a transition of the first clock signal that is substantially coincident with a transition of the second clock signal, is prevented from being latched in the second clock domain responsive to the transition of the second clock signal. The first clock signal is prevented from being latched for a time period which is greater than a maximum clock skew which may exist between the first and second clock signals.

Abstract: A method of transmitting a signal from a relatively fast clock domain to a relatively slow clock domain is described. The fast and slow clock domains operate according to respective fast and slow clock signals that are substantially synchronized and that have respective frequencies that are non-integer multiples. A first state of an input signal is latched at the commencement of a first period of the fast clock signal, the commencement of the first period of the fast clock signal being substantially coincident with the commencement of a first period of the slow clock signal. In response to the latching of the first state of the input signal, a first output signal is generated and held over the first period, and at least one further period, of the fast clock signal. The first output signal is then latched in the second time domain in response to the commencement of a second period of the slow clock signal, the second period being immediately subsequent to the first period of the slow clock signal.

Abstract: A method for controlling core logic temperature. The core logic having a memory controller and memory components coupled to system memory. The method having the step of determining access rate to the system memory through the core logic and controlling the temperature of the core logic by adjusting the access rate.