Abstract: Various implementations described herein are directed to a device having a load circuit that consumes current. The device may include a power distribution network having impedance stimulated by the load circuit. The device may include a sensing circuit that collects voltage during operation of the load circuit and reconstructs an origin current for the load circuit based on the impedance of the power distribution network and the voltage collected during operation of the load circuit.

Abstract: Various implementations described herein are directed to a device having a load circuit that consumes current. The device may include a power distribution network having impedance stimulated by the load circuit. The device may include a sensing circuit that collects voltage during operation of the load circuit and reconstructs an origin current for the load circuit based on the impedance of the power distribution network and the voltage collected during operation of the load circuit.

Abstract: Various implementations described herein are directed to device having multiple stages. The device may include a first stage that converts an analog voltage signal in a power supply domain into a digitally coded signal. The device may include a second stage that generates a derivative of the digitally coded signal, detects an event of the analog voltage signal based on the derivative of the digitally coded signal, and derives a control signal based on the event. The device may include a third stage that injects current into or sinks current from the power supply domain that is associated with the analog voltage signal based on the control signal.

Abstract: One embodiment relates to an apparatus that includes at least one circuit block and a voltage source configured to supply a first voltage to the at least one circuit block. The apparatus also includes a power delivery unit configured to be selectively activated based on a whether a quantity of power is to be delivered from the power delivery unit to the circuit block. A control unit is configured to, upon a change in power consumption of the at least one circuit block, activate the auxiliary power delivery unit to deliver the quantity of power to the circuit block. The auxiliary power delivery unit can quickly supply large currents since it does not necessarily rely on slow control loops using voltage sensing. Rather, the auxiliary power delivery unit often delivers pre-calculated current profiles to respond to the timing characteristic of the change of power consumption and of the voltage regulator.

Abstract: One embodiment relates to an apparatus that includes at least one circuit block and a voltage source configured to supply a first voltage to the at least one circuit block. The apparatus also includes a power delivery unit configured to be selectively activated based on a whether a quantity of power is to be delivered from the power delivery unit to the circuit block. A control unit is configured to, upon a change in power consumption of the at least one circuit block, activate the auxiliary power delivery unit to deliver the quantity of power to the circuit block. The auxiliary power delivery unit can quickly supply large currents since it does not necessarily rely on slow control loops using voltage sensing. Rather, the auxiliary power delivery unit often delivers pre-calculated current profiles to respond to the timing characteristic of the change of power consumption and of the voltage regulator.

Abstract: The present disclosure relates to the heating of memory cells.

Abstract: The present disclosure relates to the heating of memory cells.

Abstract: A method for waking up a circuit, comprising charging a voltage line of the circuit with a constant wake-up current until the voltage line reaches a predetermined voltage. Also, an apparatus, comprising a circuit portion, a switch configured to selectively couple an input of the circuit portion to a supply voltage, a current source configured to generate a first current, and a control circuit configured to control a state of the switch depending on the first current.

Abstract: A method for waking up a circuit, comprising charging a voltage line of the circuit with a constant wake-up current until the voltage line reaches a predetermined voltage. Also, an apparatus, comprising a circuit portion, a switch configured to selectively couple an input of the circuit portion to a supply voltage, a current source configured to generate a first current, and a control circuit configured to control a state of the switch depending on the first current.

Abstract: A method for operating a semiconductor memory cell is disclosed. A first voltage is applied to the memory cell. The first voltage is dependent on temperature and semiconductor process variation in a manner that keeps the memory cell in a stable region of operation.

Abstract: A device is provided including a memory cell, a first supply voltage generator, passively coupled to the memory cell, to provide the memory cell with a first supply voltage, and a second supply voltage generator, coupled to the memory cell, to provide the memory cell with a second supply voltage.

Abstract: A memory comprises a bitline, an accessible memory element, an activable switch coupled between the bitline and the access node and a controller configured to activate the activable switch within a first activation period, to activate the activable switch within a second activation period and to deactivate the activable switch at least once when accessing to the accessible memory element during the same access operation.

Abstract: Method and memory device for reliably writing an information value to a memory element of the memory device. A first information value is represented by a first potential and a second information value is represented by a second potential. A bit line is provided for writing either the first information value or the second information value to the memory element. A potential controller is coupled to the bit line, where the potential controller is configured to apply a third potential to the bit line, which is less than the first potential when writing the first information value to the memory element.

Abstract: A bit line dummy core-cell comprises at least a first inverter and at least a second inverter which are cross coupled to form a bistable flip-flop. The first inverter comprises a first PMOS transistor and a first NMOS transistor connected in series by means of a first internal storage node between a high reference potential and a low reference potential. The second inverter comprises a second PMOS transistor and a second NMOS transistor connected in series by means of a second internal storage node. The source of the second PMOS transistor and the second internal storage node are connected to the low reference potential so that the first internal storage node always stores a logic high level. A first access transistor is coupled between a dummy bit line providing a self-timing signal and the first internal node storing the logical high level.

Abstract: A bit line dummy core-cell comprises at least a first inverter and at least a second inverter which are cross coupled to form a bistable flip-flop. The first inverter comprises a first PMOS transistor and a first NMOS transistor connected in series by means of a first internal storage node between a high reference potential and a low reference potential. The second inverter comprises a second PMOS transistor and a second NMOS transistor connected in series by means of a second internal storage node. The source of the second PMOS transistor and the second internal storage node are connected to the low reference potential so that the first internal storage node always stores a logic high level. A first access transistor is coupled between a dummy bit line providing a self-timing signal and the first internal node storing the logical high level.

Abstract: The inventive memory circuit comprises a plurality of memory cells. The memory circuit further comprises a memory access means being controlled by at least one control signal. In addition, a control means for generating the at least one control signal is contained in the memory circuit, with the control means comprising a delay means. The delay means delays a switching of the at least one control signal. The delay time is adjustable in view of the applied supply voltage.

Abstract: A delay circuit comprises a signal generator and a delay component. The signal generator comprises a terminal for receiving a trigger signal and an output for outputting a signal when receiving a trigger signal with a pre-determined characteristic. The delay mean comprises an input for receiving the signal outputted by the signal generator and an output for generating a signal delayed with a delay referred to the time the delay mean received the signal outputted by the signal generator.

Abstract: The inventive memory circuit comprises a main memory block and a substitution memory block for substitution of defect memory cells, with the substitution memory block being external to the main memory block. The substitution memory block is arranged to substitute at least one bitline-related or wordline-related set of memory cells being connected to the same bitline or wordline, respectively. Furthermore, the inventive memory circuit comprises redirection means for redirecting the access to a memory cell of the at least one respective substituted set of memory cells to the substitution memory block.

Abstract: Method and memory device for reliably writing an information value to a memory element of the memory device. A first information value is represented by a first potential and a second information value is represented by a second potential. A bit line is provided for writing either the first information value or the second information value to the memory element. A potential controller is coupled to the bit line, where the potential controller is configured to apply a third potential to the bit line, which is less than the first potential when writing the first information value to the memory element.

Abstract: A memory comprises a bitline, an accessible memory element, an activable switch coupled between the bitline and the access node and a controller configured to activate the activable switch within a first activation period, to activate the activable switch within a second activation period and to deactivate the activable switch at least once when accessing to the accessible memory element during the same access operation.