Abstract: An integrated circuit includes a computer unit configured to execute the neural network. Parameters of the neural network are stored in a first memory. Data supplied at the input of the neural network or generated by the neural network are stored in a second memory. A first barrel shifter circuit transmits data from the second memory to the computer unit. A second barrel shifter circuit delivers data generated during the execution of the neural network by the computer unit to the second memory. A control unit is configured to control the computer unit, the first and second barrel shifter circuits, and accesses to the first memory and to the second memory.

Abstract: A method and corresponding device for processing a frequency-modulated analog signal are disclosed. The signal includes a number of symbols belonging to a set of M symbols respectively associated with at least one frequency of a set of M frequencies. The method includes a phase of reading each symbol of the signal that includes a sampling of a signal portion corresponding to the duration of a symbol and delivering N samples (M being less than N). M individual discrete Fourier transform processing operations are performed on the N samples. Each individual processing operation is associated with each of the frequencies. The M individual processing operations deliver M processing results. The value of the symbol can be determined from the M processing results.

Abstract: A method and corresponding device for processing a frequency-modulated analog signal are disclosed. The signal includes a number of symbols belonging to a set of M symbols respectively associated with at least one frequency of a set of M frequencies. The method includes a phase of reading each symbol of the signal that includes a sampling of a signal portion corresponding to the duration of a symbol and delivering N samples (M being less than N). M individual discrete Fourier transform processing operations are performed on the N samples. Each individual processing operation is associated with each of the frequencies. The M individual processing operations deliver M processing results. The value of the symbol can be determined from the M processing results.

Abstract: Method of elementary updating a check node of a non-binary LDPC code during a decoding of a block encoded with said LDPC code, comprising receiving a first input message (U) and a second input message (V) each comprising nm doublets having a symbol and an associated metric, delivering an output message (S) possessing nm output doublets by computing a matrix of nm2 combined doublets on the basis of a combination of the doublets of the two input messages (U,V), and reducing the number of the combined doublets so as to obtain the nm output doublets of the output message (S) possessing the nm largest or lowest metrics. The method further includes tagging redundant symbols within each input message (U, V) and fixing same at a reference value, the value of the metric of each combined doublet resulting from a combination of at least one doublet comprising a tagged redundant symbol.

Abstract: A low density parity check decoder for performing LDPC decoding based on a layered algorithm applied to a parity check matrix, the decoder including a channel memory, a metrics memory, first and second operand supply paths each arranged to provide operands based on channel values and metrics values; a processor block including a plurality processing units in parallel and arranged to receive operands from the first supply path and to determine updated metric values, a buffer arranged to store at least one of the operands from the first supply path; and an adder coupled to an output of the processor block and arranged to generate updated channel values by adding the updated metrics values to operands from a selected one of the buffer and the second supply path.

Abstract: A method is for decoding a block of N information items encoded with an error correction code and mutually correlated. The method includes carrying out a first decorrelation of the N information items of a block is carried out, and storing the block decorrelated. The method also includes a performing a processing for decoding a group of P information items of the block, and decorrelating at least part of the P decoded information items. The processing for decoding the group of P information items and the decorrelation are repeated with different successive groups of P information items of the block until the N information items of the block have been processed, until a decoding criterion is satisfied.

Abstract: Method of elementary updating a check node of a non-binary LDPC code during a decoding of a block encoded with said LDPC code, comprising receiving a first input message (U) and a second input message (V) each comprising nm doublets having a symbol and an associated metric, delivering an output message (S) possessing nm output doublets by computing a matrix of nm2 combined doublets on the basis of a combination of the doublets of the two input messages (U,V), and reducing the number of the combined doublets so as to obtain the nm output doublets of the output message (S) possessing the nm largest or lowest metrics. The method further includes tagging redundant symbols within each input message (U, V) and fixing same at a reference value, the value of the metric of each combined doublet resulting from a combination of at least one doublet comprising a tagged redundant symbol.

Abstract: A soft output Viterbi algorithm (SOVA) decoder arranged to decode symbols received over a transmission channel, the symbols indicating a state transition between two states of a plurality of states that determines a decoded data value, the SOVA decoder comprising a reliability memory unit including at least four stages of logic units, each logic unit including a single buffer and at least four stages including a plurality of full stages comprising a separate logic unit corresponding to each of the plurality of states; and a plurality of compact stages including half or less than half the number of logic units than the number of the plurality of states, each logic unit corresponding to two of the plurality of states.

Abstract: An electronic device includes N inputs to receive R input data, R being able to take values from 1 to N, and N outputs. A configurable shift circuit is coupled between the N inputs and N outputs and has a cascade of shift stages, each shift stage comprising at least N controllable multiplexers. Each multiplexer includes first and second elementary inputs respectively coupled to a first input and a second input taken from among the N inputs so as to, on command, not shift a data item present on the first elementary input and shift a data item present on the second elementary input by an elementary shift value dependent on a rank of the shift stage, a direction of the shift being identical for each multiplexer. Control circuitry controls the multiplexers to deliver the R input data on R outputs.

Abstract: A method is for decoding a succession of blocks of data encoded with an LDPC code. The method includes storing the blocks temporarily and successively in an input memory before decoding the blocks successively in an iterative manner, the input memory having a memory size for storage of at least two blocks, and defining a current indication representative of a threshold number of iterations for decoding a current block. The method includes decoding the current block until a decoding criterion is satisfied or so long as a number of iterations performed for decoding the current block has not reached the current indication while at least one of a first subsequent block and a part of a second subsequent block are stored in the input memory, and updating the current indication for decoding the first subsequent block as a function of the number of iterations performed for decoding the current block.

Abstract: The metrics matrix may include at least one particular layer including at least one particular column having several metrics cues, respectively, situated in different rows. For the particular layer, the updating of the channel cue is associated with the particular column involving at each iteration one updated metric cue selected from all the metrics cues of the particular column. The row of the selected metric cues may change at each iteration.

Abstract: A method is for decoding a block of N information items encoded with an error correction code and mutually correlated. The method includes carrying out a first decorrelation of the N information items of a block is carried out, and storing the block decorrelated. The method also includes a performing a processing for decoding a group of P information items of the block, and decorrelating at least part of the P decoded information items. The processing for decoding the group of P information items and the decorrelation are repeated with different successive groups of P information items of the block until the N information items of the block have been processed, until a decoding criterion is satisfied.

Abstract: Method of elementary updating a check node of a non-binary LDPC code during, comprising receiving a first input message (U) and a second input message (V) each comprising nm doublets having a symbol and an associated metric, delivering an output message (S) possessing nm output doublets by computing a matrix (M) of nm2 combined doublets on the basis of a combination of the doublets of the two input messages (U,V), and reducing the number of the combined doublets so as to obtain the nm output doublets of the output message (S) possessing the nm largest or lowest metrics. The method further includes tagging redundant symbols within each input message (U, V) and fixing same at a reference value, the value of the metric of each combined doublet resulting from a combination of at least one doublet comprising a tagged redundant symbol.

Abstract: A soft output Viterbi algorithm (SOVA) decoder arranged to decode symbols received over a transmission channel, the symbols indicating a state transition between two states of a plurality of states that determines a decoded data value, the SOVA decoder comprising a reliability memory unit including at least four stages of logic units, each logic unit including a single buffer and at least four stages including a plurality of full stages comprising a separate logic unit corresponding to each of the plurality of states; and a plurality of compact stages including half or less than half the number of logic units than the number of the plurality of states, each logic unit corresponding to two of the plurality of states.

Abstract: A method for the iterative decoding of a block of bits having a number N of bits to be decoded where N is a whole number greater than or equal to two, using an iterative decoding algorithm, comprises the generation of a current block of N intermediate decision bits by executing an iteration of the decoding algorithm, followed by the verification of a stability criterion for the current block by comparison of the current block with a given block of N reference bits. If the stability criterion is satisfied, the iterations of the iterative decoding algorithm are stopped and the current block of intermediate decision bits is delivered as a block of hard decision bits. Otherwise another iteration of the decoding algorithm is executed.

Abstract: A low density parity check decoder for performing LDPC decoding based on a layered algorithm applied to a parity check matrix, the decoder including a channel memory, a metrics memory, first and second operand supply paths each arranged to provide operands based on channel values and metrics values; a processor block including a plurality processing units in parallel and arranged to receive operands from the first supply path and to determine updated metric values, a buffer arranged to store at least one of the operands from the first supply path; and an adder coupled to an output of the processor block and arranged to generate updated channel values by adding the updated metrics values to operands from a selected one of the buffer and the second supply path.

Abstract: A device for storing blocks of bits intended to be decoded according to a block decoding algorithm. The blocks are likely to belong to a given category out of a first category and a second category. The first category corresponds to a first given block size, and the second category corresponds to at least one second given block size less than said first block size. The storage device comprises three storage elements having a size suitable for storing one block of the first category each, and at least two of which are structured to store either one block of the first category, or one block of the second category or a number of blocks of the second category simultaneously.

Abstract: An electronic device includes N inputs to receive R input data, R being able to take values from 1 to N, and N outputs. A configurable shift circuit is coupled between the N inputs and N outputs and has a cascade of shift stages, each shift stage comprising at least N controllable multiplexers. Each multiplexer includes first and second elementary inputs respectively coupled to a first input and a second input taken from among the N inputs so as to, on command, not shift a data item present on the first elementary input and shift a data item present on the second elementary input by an elementary shift value dependent on a rank of the shift stage, a direction of the shift being identical for each multiplexer. Control circuitry controls the multiplexers to deliver the R input data on R outputs.

Abstract: The electronic shift device includes N inputs and N outputs, a configurable barrel shifter connected between the N inputs and the N outputs. A second shifter is arranged and connected between some of the outputs of the barrel shifter and some of the N outputs according to different predetermined organizations of data that can be received simultaneously on at least some of the N inputs. The second shifter is configurable so that, for a relevant organization and regardless of the desired shift value compatible with the organization, the corresponding input data are delivered to predetermined outputs. A first controller is able to configure the barrel shifter according to the desired shift value and a second controller is able to configure the second shifter according to the organization of the data that can actually be received and according to the desired shift value.

Abstract: The metrics matrix may include at least one particular layer including at least one particular column having several metrics cues, respectively, situated in different rows. For the particular layers the updating of the channel cue is associated with the particular column involving at each iteration one updated metric cue selected from all the metrics cues of the particular column. The row of the selected metric cues may change at each iteration.