Abstract: Disclosed is a deglitcher circuit having a programmable hysteresis. The deglitcher samples a received input signal, wherein the input signal may include one or more glitches. Responsive to a change in state of the sampled input signal, the deglitcher counts the number of samples of the changed state of the input signal. The count value increments with each sampled changed state, and decrements with each sampled original state of the input signal. When the count value reaches a threshold, the state of the output signal is changed. The output signal of the disclosed deglitcher circuit provides an accurate, glitch-free reconstruction of the sampled input signal. Additionally, the disclosed deglitcher circuit reduces the number of memory elements required for a given number of samples of the input signal, thereby allowing for a larger number of samples to be taken without necessarily having to increase the memory elements required by the deglitcher.

Abstract: Disclosed is a programmable pulse width discriminator circuit operable to receive a set of parameters from a user and indicate when an input signal satisfies conditions set by the user-defined parameters. The input signal is sampled by the pulse width discriminator circuit to detect a desired state of the input signal. The user may set the parameters such that the pulse width discriminator indicates the condition wherein the number of consecutive samples for which the input signal is the desired state is (i) greater than a first threshold value, (ii) less than a second threshold value, or (iii) between the first and second threshold values. In these embodiments, the user sets the first and second threshold values and selects which set of conditions are indicated by the output of the circuit.

Abstract: Disclosed is a programmable pulse width discriminator circuit operable to receive a set of parameters from a user and indicate when an input signal satisfies conditions set by the user-defined parameters. The input signal is sampled by the pulse width discriminator circuit to detect a desired state of the input signal. The user may set the parameters such that the pulse width discriminator indicates the condition wherein the number of consecutive samples for which the input signal is the desired state is (i) greater than a first threshold value, (ii) less than a second threshold value, or (iii) between the first and second threshold values. In these embodiments, the user sets the first and second threshold values and selects which set of conditions are indicated by the output of the circuit.

Abstract: Disclosed is a programmable pulse width discriminator circuit operable to receive a set of parameters from a user and indicate when an input signal satisfies conditions set by the user-defined parameters. The input signal is sampled by the pulse width discriminator circuit to detect a desired state of the input signal. The user may set the parameters such that the pulse width discriminator indicates the condition wherein the number of consecutive samples for which the input signal is the desired state is (i) greater than a first threshold value, (ii) less than a second threshold value, or (iii) between the first and second threshold values. In these embodiments, the user sets the first and second threshold values and selects which set of conditions are indicated by the output of the circuit.

Abstract: Disclosed is a deglitcher circuit having a programmable hysteresis. The deglitcher samples a received input signal, wherein the input signal may include one or more glitches. Responsive to a change in state of the sampled input signal, the deglitcher counts the number of samples of the changed state of the input signal. The count value increments with each sampled changed state, and decrements with each sampled original state of the input signal. When the count value reaches a threshold, the state of the output signal is changed. The output signal of the disclosed deglitcher circuit provides an accurate, glitch-free reconstruction of the sampled input signal. Additionally, the disclosed deglitcher circuit reduces the number of memory elements required for a given number of samples of the input signal, thereby allowing for a larger number of samples to be taken without necessarily having to increase the memory elements required by the deglitcher.

Abstract: A serial in random out memory circuit has a number of memory cells integrated with write control circuitry for writing a sequence of data inputs to sequential locations in the memory cells. Read control circuitry is integrated to receive address signals from an external device and provide a random access read output from the memory cells, mapped into an address range of the external device. Compared to circuits using discrete components and conventional RAM chips, the integrated SIRO can enable some of the circuitry or external software to be dispensed with and so reduce costs or increase performance. The memory cells can be arranged in a number of blocks, selectable one at a time for mapping to the external device address range.

Abstract: A key switch matrix circuit includes key switches arranged in rows and columns, each row having a scan line, each column having a sense line. Each key switch is operable to couple a scan line to a sense line. A scan signal delivery circuit supplies scan signals to the scan lines, the scan signals delivering a scan pulse to each row of the key switch matrix circuit in turn. A key switch detection circuit outputs a first signal if a key switch is operated and a scan pulse detection circuit outputs a second signal if a scan pulse is coupled to a sense line. The scan signal delivery circuit begins supplying scan signals in response to the first signal and stops supplying scan signals in response to the second signal. In one embodiment, a processor reads the sense lines in response to the second signal.

Abstract: A key switch matrix circuit includes key switches arranged in rows and columns, each row having a scan line, each column having a sense line. Each key switch is operable to couple a scan line to a sense line. A scan signal delivery circuit supplies scan signals to the scan lines, the scan signals delivering a scan pulse to each row of the key switch matrix circuit in turn. A key switch detection circuit outputs a first signal if a key switch is operated and a scan pulse detection circuit outputs a second signal if a scan pulse is coupled to a sense line. The scan signal delivery circuit begins supplying scan signals in response to the first signal and stops supplying scan signals in response to the second signal. In one embodiment, a processor reads the sense lines in response to the second signal.

Abstract: Circuits and methods for supplying a temporary power supply at a predetermined voltage. A circuit includes a first DC/DC voltage converter that receives an input from a power supply at a first voltage level and generates an output at a second voltage level, higher than the first voltage level. The output is provided to charge a capacitor. A second DC/DC voltage converter has an input connected to the capacitor for drawing power from the capacitor at the second voltage level and generating an output voltage less than the second voltage level. The second DC/DC voltage converter further includes a feedback input that monitors the circuit's output voltage and activates the second DC/DC voltage converter when the output voltage falls below a predetermined threshold.

Abstract: A serial in random out memory circuit has a number of memory cells integrated with write control circuitry for writing a sequence of data inputs to sequential locations in the memory cells. Read control circuitry is integrated to receive address signals from an external device and provide a random access read output from the memory cells, mapped into an address range of the external device. Compared to circuits using discrete components and conventional RAM chips, the integrated SIRO can enable some of the circuitry or external software to be dispensed with and so reduce costs or increase performance. The memory cells can be arranged in a number of blocks, selectable one at a time for mapping to the external device address range.

Abstract: Circuits and methods for supplying a temporary power supply at a predetermined voltage. A circuit includes a first DC/DC voltage converter that receives an input from a power supply at a first voltage level and generates an output at a second voltage level, higher than the first voltage level. The output is provided to charge a capacitor. A second DC/DC voltage converter has an input connected to the capacitor for drawing power from the capacitor at the second voltage level and generating an output voltage less than the second voltage level. The second DC/DC voltage converter further includes a feedback input that monitors the circuit's output voltage and activates the second DC/DC voltage converter when the output voltage falls below a predetermined threshold.

Abstract: Circuits and methods for supplying a temporary power supply at a predetermined voltage are disclosed. A circuit includes first DC/DC voltage that receives an input from a power supply at a first voltage level and generates an output at a second voltage level, higher than the first voltage level. The output is provided to charge a capacitor. A second DC/DC voltage converter has an input connected to the capacitor for drawing power from the capacitor at the second voltage level and an generates an output voltage less than the second voltage level. The second DC/DC voltage converter further includes a feedback input that monitors the circuit's output voltage and activates the second DC/DC voltage converter when the output voltage falls below a predetermined threshold.

Abstract: Circuits and methods for supplying a temporary power supply at a predetermined voltage are disclosed. A circuit includes first DC/DC voltage that receives an input from a power supply at a first voltage level and generates an output at a second voltage level, higher than the first voltage level. The output is provided to charge a capacitor. A second DC/DC voltage converter has an input connected to the capacitor for drawing power from the capacitor at the second voltage level and an generates an output voltage less than the second voltage level. The second DC/DC voltage converter further includes a feedback input that monitors the circuit's output voltage and activates the second DC/DC voltage converter when the output voltage falls below a predetermined threshold.

Abstract: Circuits and methods for generating a reset signal are disclosed. A reset driver circuit receives a reset signal from a circuit, e.g., a reset generator and an input signal indicative of a required characteristic of a reset signal for a second circuit. The reset driver compares a characteristic of the reset signal with the input signal indicative of a required characteristic of a reset signal for a second circuit and generates an output signal that includes the required characteristics of the reset signal for a second circuit. A reset driver circuit may be placed in a communication path between a conventional reset generator and a second circuit that requires a reset signal.