Abstract: A pressure sensing device including an elongate housing configured to be at least partially inserted into a user, and that defines an external surface having a proximal end and a distal end defining a longitudinal axis therebetween. The device includes a first pressure sensor, configured to sense pressure applied to a first portion of the external surface and to convert the sensed pressure to first pressure data, and a second pressure sensor, configured to sense pressure applied to a second portion of the external surface and to convert the sensed pressure to second pressure data. Sensor is spaced, along the longitudinal axis, toward the distal end from sensor.

Abstract: The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.

Abstract: The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.

Abstract: The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.

Abstract: A method for forming a package-on-package structure is disclosed. The method comprises the step of providing a first semiconductor package. The first semiconductor package has at least one encapsulation layer formed on at least one side of the first semiconductor package. The method also involves the step of securing the first semiconductor package to a surface. The surface is adapted for receiving the first semiconductor package. The method further involves the step of reducing the thickness of the at least one encapsulation layer to a predetermined thickness. The at least one encapsulation layer having a portion distal the surface removed. More specifically, the thickness of the at least one encapsulation layer is reduced for providing a predetermined clearance from a second semiconductor package attachable to the first semiconductor package.

Abstract: A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with first and second regions with a first device layer. A second device layer including nanocrystals is also formed. A cover layer is provided over the second device layer. The cover layer is patterned to expose portions of the second device layer in the first and second regions. The exposed portions of the second device layer in the first and second regions are processed to form modified portions. The processing of the exposed portions at least reduces the nanocrystals to a diameter below a threshold diameter in the modified portions. The modified portions are removed.

Abstract: A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with first and second regions with a first device layer. A second device layer including nanocrystals is also formed. A cover layer is provided over the second device layer. The cover layer is patterned to expose portions of the second device layer in the first and second regions. The exposed portions of the second device layer in the first and second regions are processed to form modified portions. The processing of the exposed portions at least reduces the nanocrystals to a diameter below a threshold diameter in the modified portions. The modified portions are removed.

Abstract: A method for forming a package-on-package structure is disclosed. The method comprises the step of providing a first semiconductor package. The first semiconductor package has at least one encapsulation layer formed on at least one side of the first semiconductor package. The method also involves the step of securing the first semiconductor package to a surface. The surface is adapted for receiving the first semiconductor package. The method further involves the step of reducing the thickness of the at least one encapsulation layer to a predetermined thickness. The at least one encapsulation layer having a portion distal the surface removed. More specifically, the thickness of the at least one encapsulation layer is reduced for providing a predetermined clearance from a second semiconductor package attachable to the first semiconductor package.

Abstract: A method (and semiconductor device) of fabricating a semiconductor device provides a shallow trench isolation (STI) structure or region by implanting ions in the STI region. After implantation, the region (of substrate material and ions of a different element) is thermally annealed producing a dielectric material operable for isolating two adjacent field-effect transistors (FET). This eliminates the conventional steps of removing substrate material to form the trench and refilling the trench with dielectric material. Implantation of nitrogen ions into an STI region adjacent a p-type FET applies a compressive stress to the transistor channel region to enhance transistor performance. Implantation of oxygen ions into an STI region adjacent an n-type FET applies a tensile stress to the transistor channel region to enhance transistor performance.

Abstract: The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.

Abstract: Devices with embedded silicon or germanium nanocrystals, fabricated using ion implantation, exhibit superior data-retention characteristics relative to conventional floating-gate devices. However, the prior art use of ion implantation for their manufacture introduces several problems. These have been overcome by initial use of rapid thermal oxidation to grow a high quality layer of thin tunnel oxide. Chemical vapor deposition is then used to deposit a germanium doped oxide layer. A capping oxide is then deposited following which the structure is rapid thermally annealed to synthesize the germanium nanocrystals.

Abstract: Methods, systems and devices are presented that provide improved medical diagnostic and intervention procedures such as magnetic resonance imaging, cardiac imaging, cardiac nuclear scintigraphy, computed tomography, echocardiography, imaging to direct laser ablation, imaging to direct radio frequency radiation ablation, imaging to direct gamma knife radiation therapy, and imaging to direct radiation therapy by respiratory gating. In a preferred embodiment, one or more balloon pressure probes within a catheter are placed into the esophagus and detect pressure within the esophagus to infer respiratory air-flow. Other probes such as those based on fiber optics and other useful materials are described. Many of these devices interact poorly or not at all with magnetic and electromagnetic fields, and are particularly useful for use in respiratory gating of MRI.

Abstract: The present invention includes a method and apparatus for high sensitivity whole body scanning using MR imaging. The invention includes acquiring MR data as the patient moves through the iso-center of the magnet while providing interactive control for the operator to change scan parameters and table motion and direction. The technique allows efficient whole body scanning for fast screening of abnormalities while allowing operator control during the screening process to interrupt table motion and redirect the speed and direction of the table while also allowing control over the acquisition plane, number of sections imaged, inter-section spacing, and the scan location.

Abstract: Methods for improving spatial and/or temporal resolution of digital images and for improving image data transmission by a novel technique—back pixelation, which involves data processing and reconstruction of overlaid images from multiple acquisition or multiple sampling. The back pixelation technique may be used for image data acquisition and transmission; it may be applied prospectively or retrospectively. In particular, the methods of this invention may be used in reducing the pixel size of a two-dimensional image or the voxel size of a three dimensional image; producing a two- or three-dimensional image from a multiplicity of images acquired from an object which are capable of overlaying one another by an increment; producing and transmitting a two- or three-dimensional image by multiple acquisitions according to an acquisition matrix; or transmitting a two- or three-dimensional image by reducing or decomposing the image to a plurality of image data packets and transmitting the same.

Abstract: Devices with embedded silicon or germanium nanocrystals, fabricated using ion implantation, exhibit superior data-retention characteristics relative to conventional floating-gate devices. However, the prior art use of ion implantation for their manufacture introduces several problems. These have been overcome by initial use of rapid thermal oxidation to grow a high quality layer of thin tunnel oxide. Chemical vapor deposition is then used to deposit a germanium doped oxide layer. A capping oxide is then deposited following which the structure is rapid thermally annealed to synthesize the germanium nanocrystals.