Abstract: An integrated circuit package may include a package substrate having a surface, first interconnects of a first size that are arranged in a substantially circular shape that is centered on the surface of the package substrate, and second interconnects of a second size that is different from the first size, where the second interconnects are arranged in a ring shape on the surface of the package substrate. The ring shape of the second interconnects is concentric with the substantially circular shape of the first interconnects. The integrated circuit package may further include third interconnects of a third size that are arranged in peripheral corner regions on the surface of the package substrate. The third size may be smaller or bigger than at least one of the first and second sizes.

Abstract: A coreless organic substrate in which a mounting hole is formed near each corner of the substrate and is used during assembly processes to secure the substrate so as to prevent flexing.

Abstract: Integrated circuit packages with enhanced thermal conduction are disclosed. A disclosed integrated circuit package includes a package substrate. An integrated circuit die with a layer of metal on its backside is mounted on the package substrate at a first temperature (e.g., reflow temperature). The package further includes a heat spreading lid that is bonded to the integrated circuit die at a second temperature, which is less than the first temperature. The heat spreading lid is formed over the integrated circuit die in which the heat spreading lid makes physical contact with the integrated circuit die via the layer of metal.

Abstract: A method of manufacturing an integrated circuit package substrate is disclosed. The method may include forming a hole through a substrate layer in the package substrate. The method also includes inserting a prefabricated coaxial wire segment into the hole. The prefabricated coaxial wire segment may include a signal conductor, a ground conductor that surrounds the signal conductor, and dielectric material interposed between the signal conductor and the ground conductor. Furthermore, an integrated circuit package is also disclosed.

Abstract: A semiconductor integrated circuit is mounted on the package substrate so that its sides are at approximately a 45 degree angle to the sides of the substrate. As a result, the sides of the die face the corners of the substrate rather than the sides of the substrate. In this orientation, substantially all the space available in the corners of the substrate becomes readily available for use in reducing congestion along the sides of the die and/or routing connections to the die and/or in mounting coupling capacitors. It also becomes possible to mount a larger die on the substrate while still meeting manufacturing and reliability rules. Larger stiffener/lid structures may also be used for enhanced adhesion to the substrate.

Abstract: A Ball Grid Array (BGA) integrated circuit package having (i) an additional dedicated ground ring on the package substrate which provides a reduced area return current loop path to reduce wire bond inductance; and/or (ii) ground wires positioned between adjacent input/output wires on the substrate which provide additional transient current paths among the input/output wires for improved characteristic impedance and cross talk control.

Abstract: The present invention comprises a substrate, an integrated circuit mounted on the substrate, a passive component such as a capacitor mounted on the integrated circuit, and an encapsulation enclosing the integrated circuit and the passive component. The integrated circuit can be mounted in a flip-chip configuration with its active side facing the substrate and the passive component mounted on its backside or with its active side up with its backside on the substrate and the passive component mounted on the active side of the integrated circuit.

Abstract: Techniques for integrated circuit packaging in a flip chip configuration that ensures a migration path between related integrated circuits and utilizes core I/O (or area I/O) are provided. An integrated circuit, having a superset of functional circuit elements as compared to a reference integrated circuit, includes first and second sets of interconnection elements to connect to a package substrate. The first and second sets have matching arrangements, and corresponding interconnection elements of the first and second set have consistent functional assignments. The first and second sets include interconnection elements of mixed functional assignments. The first set is disposed within an area matching a size and shape of the reference integrated circuit, while the second set is disposed outside the area. In a specific embodiment, the first set includes an I/O signal and is located in the core area.

Abstract: Methods and apparatus are provided for designing the electrical interconnects of a substrate. Modules are used to design sections of the electrical interconnects. Multiple modules may be interconnected to generate the electrical interconnects. The placement of modules and/or the interconnection of the modules may depend on a netlist and/or a separate report. Modules may even be defined by various constraints. Accordingly, a module based design may be implemented for efficiently and effectively producing a standardized electrical interconnect design.

Abstract: The present invention provides a heat spreader with a bypass capacitor to provide substantially instant power and/or to control simultaneous switching noise (SSN). The present invention also provides a semiconductor device package incorporating this heat spreader. In addition, fabrication methods for such heat spreaders and packages are provided. Generally, the heat spreaders and packages of the present invention include an embedded bypass capacitor that can provide decoupling capacitance in order to deliver near instant power to the die and/or minimize SSN. In a preferred embodiment, the embedded bypass capacitor is connected to terminals integrated with the heat spreader (e.g., lid; stiffener) and/or to a package plane (e.g., power plane or ground plane) in the package substrate for connection via the flip chip package's power delivery system to a power source and/or component.

Abstract: The present invention includes a semiconductor package and a method of making the semiconductor package. The semiconductor package comprises an IC chip and a substrate, wherein part of the substrate routing such as substrate level trace routing is placed on the IC chip using post-passivation thick metal process at wafer level.