Abstract: An apparatus and method for selecting the operation of digital data ports for regulating information flow between a programmable serial-bit, microinstruction processor and a multiplicity of peripheral devices connected to the processor is provided by a control pulse distribution circuit operating in conjunction with a controllable decoder circuit. Peripheral device designation instructions which may be available from the processor may define which of the ports will function, i.e., be "open", within the current processor cycle to enable communications between the processor and a device connected thereto. These designation instructions may be decoded to produce enabling signals for controlling the distribution of the timing and other associated pulses needed for the activation of a port. Operation of the selection apparatus may be as to permit data flow during a specified portion of each processor cycle.

Abstract: For a serial-bit, programmable microinstruction processor having serial-byte internal transfers, an expanded-memory addressing apparatus and method is provided by the incorporation into the processor system a plurality of external memory units and a selection and transfer circuitry for accessing external memory space from within the processor. The accessing of external memory locations may be controlled by programmed memory access command instructions. These instructions may be operated upon by decoding components and buffer storage components to make available, concurrently, the entire contents of a particular one of the external memory units. Once a particular memory, or page is selected, a location within that page may then be addressed by memory address registers within the base processor.