Patents by Inventor Vincent Jarry

Vincent Jarry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11575172
    Abstract: An electronic device includes a base substrate with a mica substrate thereon. A top face of the mica substrate has a surface area smaller than a surface area of a top face of the base substrate. An active battery layer is on the mica substrate and has a top face with a surface area smaller than a surface area of a top face of the mica substrate. An adhesive layer is over the active battery layer, mica substrate, and base substrate. An aluminum film layer is over the adhesive layer, and an insulating polyethylene terephthalate (PET) layer is over the aluminum film layer. A battery pad is on the mica substrate adjacent the active battery layer, and a conductive via extends to the battery pad. A conductive pad is connected to the conductive via. The adhesive, aluminum film, and PET have a hole defined therein exposing the conductive pad.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: February 7, 2023
    Assignee: STMicroelectronics (Tours) SAS
    Inventor: Vincent Jarry
  • Publication number: 20220131215
    Abstract: An electronic device includes a base substrate with a mica substrate thereon. A top face of the mica substrate has a surface area smaller than a surface area of a top face of the base substrate. An active battery layer is on the mica substrate and has a top face with a surface area smaller than a surface area of a top face of the mica substrate. An adhesive layer is over the active battery layer, mica substrate, and base substrate. An aluminum film layer is over the adhesive layer, and an insulating polyethylene terephthalate (PET) layer is over the aluminum film layer. A battery pad is on the mica substrate adjacent the active battery layer, and a conductive via extends to the battery pad. A conductive pad is connected to the conductive via. The adhesive, aluminum film, and PET have a hole defined therein exposing the conductive pad.
    Type: Application
    Filed: January 5, 2022
    Publication date: April 28, 2022
    Applicant: STMicroelectronics (Tours) SAS
    Inventor: Vincent JARRY
  • Patent number: 11251478
    Abstract: An electronic device includes a base substrate, and a plurality of battery substrates constructed from mica and being attached to the base substrate. An aggregate area of the base substrate is greater than an aggregate area of the plurality of battery substrates. The electronic device also includes a plurality of active battery layers, each active battery layer being attached to a different respective battery substrate, with each active battery layer having a smaller area than its corresponding battery substrate. A film is disposed over the plurality of active battery layers and sized such that the film extends beyond each active battery layer to contact each battery substrate, and such that the film extends beyond each battery substrate to contact the base substrate.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: February 15, 2022
    Assignee: STMicroelectronics (Tours) SAS
    Inventor: Vincent Jarry
  • Patent number: 10444002
    Abstract: A feeler device for geometrically controlling parts, capable of determining the position of a feeler member when it comes into contact with a part to be controlled. The feeler device includes a motorized contact rod movable in translation inside a housing and a microcontroller for controlling the movement of the rod. The contact rod is driven in translation by friction with an element linked to the rotary shaft of a motor, and the contact rod cooperates with a magnetic sensor in order to detect the position of same.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: October 15, 2019
    Assignee: ACTIMESURE
    Inventors: Samuel Tregret, Philippe Prunet, Vincent Jarry
  • Publication number: 20190229302
    Abstract: An electronic device includes a base substrate, and a plurality of battery substrates constructed from mica and being attached to the base substrate. An aggregate area of the base substrate is greater than an aggregate area of the plurality of battery substrates. The electronic device also includes a plurality of active battery layers, each active battery layer being attached to a different respective battery substrate, with each active battery layer having a smaller area than its corresponding battery substrate. A film is disposed over the plurality of active battery layers and sized such that the film extends beyond each active battery layer to contact each battery substrate, and such that the film extends beyond each battery substrate to contact the base substrate.
    Type: Application
    Filed: April 2, 2019
    Publication date: July 25, 2019
    Applicant: STMicroelectronics (Tours) SAS
    Inventor: Vincent JARRY
  • Patent number: 10290838
    Abstract: A battery encapsulation method includes disposing an active battery layer on each of a plurality of battery substrates, with each battery substrate having a greater area than its corresponding active battery layer. The plurality of battery substrates are attached to an interposer having a greater area than an aggregate area of the plurality of battery substrates. The active battery layers are environmentally sealed by disposing a film over the active battery layers sized such that the film extends beyond the active battery layers to contact the battery substrates and the interposer. The interposer is physically along locations where the film contacts the interposer so as to form a plurality of battery units, with each battery unit including one of the battery substrates with the associated active battery layer disposed thereon and being environmentally sealed by the film.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: May 14, 2019
    Assignee: STMicroelectronics (Tours) SAS
    Inventor: Vincent Jarry
  • Publication number: 20190011245
    Abstract: A feeler device for geometrically controlling parts, capable of determining the position of a feeler member when it comes into contact with a part to be controlled. The feeler device includes a motorized contact rod movable in translation inside a housing and a microcontroller for controlling the movement of the rod. The contact rod is driven in translation by friction with an element linked to the rotary shaft of a motor, and the contact rod cooperates with a magnetic sensor in order to detect the position of same.
    Type: Application
    Filed: July 23, 2015
    Publication date: January 10, 2019
    Inventors: Samuel Tregret, Philippe Prunet, Vincent Jarry
  • Publication number: 20170069883
    Abstract: A battery encapsulation method includes disposing an active battery layer on each of a plurality of battery substrates, with each battery substrate having a greater area than its corresponding active battery layer. The plurality of battery substrates are attached to an interposer having a greater area than an aggregate area of the plurality of battery substrates. The active battery layers are environmentally sealed by disposing a film over the active battery layers sized such that the film extends beyond the active battery layers to contact the battery substrates and the interposer. The interposer is physically along locations where the film contacts the interposer so as to form a plurality of battery units, with each battery unit including one of the battery substrates with the associated active battery layer disposed thereon and being environmentally sealed by the film.
    Type: Application
    Filed: September 8, 2015
    Publication date: March 9, 2017
    Applicant: STMicroelectronics (Tours) SAS
    Inventor: Vincent Jarry
  • Publication number: 20160240864
    Abstract: A method for forming a microbattery including, on a surface of a first substrate, one active battery element and two contact pads, this method including the steps of: a) forming, on a surface of a second substrate, two contact pads with a spacing compatible with the spacing of the pads of the first substrate; and b) arranging the first substrate on the second substrate so that the surfaces face each other and that the pads of the first substrate at least partially superpose to those of the second substrate, where a portion of the pads of the second substrate is not covered by the first substrate.
    Type: Application
    Filed: April 29, 2016
    Publication date: August 18, 2016
    Inventor: Vincent JARRY
  • Patent number: 9356310
    Abstract: A method for forming a microbattery including, on a surface of a first substrate, one active battery element and two contact pads, this method including the steps of: a) forming, on a surface of a second substrate, two contact pads with a spacing compatible with the spacing of the pads of the first substrate; and b) arranging the first substrate on the second substrate so that the surfaces face each other and that the pads of the first substrate at least partially superpose to those of the second substrate, where a portion of the pads of the second substrate is not covered by the first substrate.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: May 31, 2016
    Assignee: STMICROELECTRONICS (TOURS) SAS
    Inventor: Vincent Jarry
  • Patent number: 8785297
    Abstract: A method for encapsulating electronic components, including the steps of: forming, in a first surface of a semiconductor wafer, electronic components; forming, on the first surface, an interconnection stack including conductive tracks and vias separated by an insulating material; forming first and second bonding pads on the interconnection stack; thinning down the wafer, except at least on its contour; filling the thinned-down region with a first resin layer; arranging at least one first chip on the first bonding pads and forming solder bumps on the second bonding pads; depositing a second resin layer covering the first chips and partially covering the solder bumps; bonding an adhesive strip on the first resin layer; and scribing the structure into individual chips.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: July 22, 2014
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Marc Feron, Vincent Jarry, Laurent Barreau
  • Patent number: 8772134
    Abstract: A method for manufacturing semiconductor chips from a semiconductor wafer, including the steps of: fastening, on a first support frame, a second support frame having outer dimensions smaller than the outer dimensions of the first frame and greater than the inner dimensions of the first frame; arranging the wafer on a surface of a film stretched on the second frame; carrying out wafer processing operations by using equipment capable of receiving the first frame; separating the second frame from the first frame and removing the first frame; and carrying out wafer processing operations by using equipment capable of receiving the second frame.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: July 8, 2014
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Vincent Jarry, Patrick Hougron, Dominique Touzet, José Mendez
  • Patent number: 8486763
    Abstract: A method for thinning and dicing a wafer of electronic circuits, wherein: a thinning step is carried out while the wafer is supported by a first film bonded at the periphery of a support frame; and a dicing step is carried out while the thinned wafer is supported by a second film bonded at the periphery of the same frame from the other surface of the wafer, the first film being unstuck only once the second one is in place.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: July 16, 2013
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Vincent Jarry, Marc Feron
  • Patent number: 8409967
    Abstract: A method for manufacturing semiconductor chips from a semiconductor wafer, including the steps of: fastening, on a first support frame, a second support frame having outer dimensions smaller than the outer dimensions of the first frame and greater than the inner dimensions of the first frame; arranging the wafer on a surface of a film stretched on the second frame; carrying out wafer processing operations by using equipment capable of receiving the first frame; separating the second frame from the first frame and removing the first frame; and carrying out wafer processing operations by using equipment capable of receiving the second frame.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: April 2, 2013
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Vincent Jarry, Patrick Hougron, Dominique Touzet, José Mendez
  • Publication number: 20130043586
    Abstract: A method for encapsulating electronic components, including the steps of: forming, in a first surface of a semiconductor wafer, electronic components; forming, on the first surface, an interconnection stack including conductive tracks and vias separated by an insulating material; forming first and second bonding pads on the interconnection stack; thinning down the wafer, except at least on its contour; filling the thinned-down region with a first resin layer; arranging at least one first chip on the first bonding pads and forming solder bumps on the second bonding pads; depositing a second resin layer covering the first chips and partially covering the solder bumps; bonding an adhesive strip on the first resin layer; and scribing the structure into individual chips.
    Type: Application
    Filed: October 11, 2012
    Publication date: February 21, 2013
    Applicant: STMicroelectronics (Tours) SAS
    Inventors: Marc Feron, Vincent Jarry, Laurent Barreau
  • Patent number: 8319339
    Abstract: A silicon chip surface mounted via balls attached to its front surface, wherein the front and rear surfaces of the chip are covered with a thermosetting epoxy resin having the following characteristics: the resin contains a proportion ranging from 45 to 60% by weight of a load formed of carbon fiber particles with a maximum size of 20 ?m and with its largest portion having a diameter ranging between 2 and 8 ?m, on the front surface side, the loaded resin covers from 45 to 60% of the ball height, on the rear surface side, the loaded resin has a thickness ranging between 80 and 150 ?m.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: November 27, 2012
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Christophe Serre, Laurent Barreau, Vincent Jarry, Patrick Hougron
  • Patent number: 8309403
    Abstract: A method for encapsulating electronic components, including the steps of: forming, in a first surface of a semiconductor wafer, electronic components; forming, on the first surface, an interconnection stack including conductive tracks and vias separated by an insulating material; forming first and second bonding pads on the interconnection stack; thinning down the wafer, except at least on its contour; filling the thinned-down region with a first resin layer; arranging at least one first chip on the first bonding pads and forming solder bumps on the second bonding pads; depositing a second resin layer covering the first chips and partially covering the solder bumps; bonding an adhesive strip on the first resin layer; and scribing the structure into individual chips.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: November 13, 2012
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Marc Feron, Vincent Jarry, Laurent Barreau
  • Publication number: 20120149174
    Abstract: A method for thinning and dicing a wafer of electronic circuits, wherein: a thinning step is carried out while the wafer is supported by a first film bonded at the periphery of a support frame; and a dicing step is carried out while the thinned wafer is supported by a second film bonded at the periphery of the same frame from the other surface of the wafer, the first film being unstuck only once the second one is in place.
    Type: Application
    Filed: December 7, 2011
    Publication date: June 14, 2012
    Inventors: Vincent Jarry, Marc Feron
  • Publication number: 20120009763
    Abstract: A method for manufacturing semiconductor chips from a semiconductor wafer, including the steps of: a) arranging the wafer on a surface of an elastic film stretched on a first support frame having dimensions much greater than the wafer dimensions, so that, in top view, a ring-shaped film portion separates this outer contour from the inner contour of the frame; b) performing manufacturing operations by using equipment capable of receiving the first frame; c) arranging, on the ring-shaped film portion, a second frame of outer dimensions smaller than the inner dimensions of the first frame; d) cutting the film between the outer contour of the second frame and the inner contour of the first frame and removing the first frame; and e) performing manufacturing operations by using equipment capable of receiving the second frame.
    Type: Application
    Filed: May 11, 2011
    Publication date: January 12, 2012
    Applicant: STMicroelectronics (Tours) SAS
    Inventor: Vincent Jarry
  • Publication number: 20110300647
    Abstract: A method for manufacturing semiconductor chips from a semiconductor wafer, including the steps of: fastening, on a first support frame, a second support frame having outer dimensions smaller than the outer dimensions of the first frame and greater than the inner dimensions of the first frame; arranging the wafer on a surface of a film stretched on the second frame; carrying out wafer processing operations by using equipment capable of receiving the first frame; separating the second frame from the first frame and removing the first frame; and carrying out wafer processing operations by using equipment capable of receiving the second frame.
    Type: Application
    Filed: June 6, 2011
    Publication date: December 8, 2011
    Applicant: STMicroelectronics (Tours) SAS
    Inventors: Vincent Jarry, Patrick Hougron, Dominique Touzet, José Mendez