Patents by Inventor Vincent John Smoral
Vincent John Smoral has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5963745Abstract: A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processor memory elements on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. The architecture uses all the pins for networking. Each chip has eight 16 bit processors, and eight respective 32K memories. I/O has three internal ports and one external port shared by the plural processors on the chip. Significant software flexibility is provided to enable quick implementation of existing programs written in common languages. The scalable chip has internal and external connections for broadcast and asynchronous SIMD, MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes.Type: GrantFiled: April 27, 1995Date of Patent: October 5, 1999Assignee: International Business Machines CorporationInventors: Clive Allan Collins, Michael Charles Dapp, James Warren Dieffenderfer, David Christopher Kuchinski, Billy Jack Knowles, Richard Edward Nier, Eric Eugene Retter, Robert Reist Richardson, David Bruce Rolfe, Vincent John Smoral
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Patent number: 5963746Abstract: A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip.Type: GrantFiled: June 6, 1995Date of Patent: October 5, 1999Assignee: International Business Machines CorporationInventors: Thomas Norman Barker, Clive Allan Collins, Michael Charles Dapp, James Warren Dieffenderfer, Billy Jack Knowles, Donald Michael Lesmeister, Richard Ernest Miles, Richard Edward Nier, Robert Reist Richardson, David Bruce Rolfe, Vincent John Smoral
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Patent number: 5842031Abstract: A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.Type: GrantFiled: June 6, 1995Date of Patent: November 24, 1998Assignee: International Business Machines CorporationInventors: Thomas Norman Barker, Clive Allan Collins, Michael Charles Dapp, James Warren Dieffenderfer, Donald George Grice, Peter Michael Kogge, David Christoper Kuchinski, Billy Jack Knowles, Donald Michael Lesmeister, Richard Ernest Miles, Richard Edward Nier, Eric Eugene Retter, Robert Reist Richardson, David Bruce Rolfe, Nicholas Jerome Schoonover, Vincent John Smoral, James Robert Stupp, Paul Amba Wilkinson
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Patent number: 5765012Abstract: A controller for a SIMD processor array that can execute instructions within each processing element is described. This three stage hierarchical controller executes instructions at the function, routine, and micro-level, to maximize the effectiveness of processing within the array elements themselves. The routine sequencer is hardwired to perform looping and flow control operations using DO/WHILE, IF/THEN/ELSE, and GO-SUB constructs. A pipeline is provided to maintain a steady flow of commands to the array, and means is provided to monitor command execution progress and to provide feedback of progress to the stages of the controller.Type: GrantFiled: August 18, 1994Date of Patent: June 9, 1998Assignee: International Business Machines CorporationInventors: Paul Amba Wilkinson, Thomas Norman Barker, James Warren Dieffenderfer, Peter Michael Kogge, Donald Michael Lesmeister, Robert Reist Richardson, Vincent John Smoral
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Patent number: 5734921Abstract: A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32 K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip.Type: GrantFiled: September 30, 1996Date of Patent: March 31, 1998Assignee: International Business Machines CorporationInventors: Michael Charles Dapp, James Warren Dieffenderfer, Richard Ernest Miles, Richard Edward Nier, Vincent John Smoral, James Robert Stupp
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Patent number: 5717943Abstract: A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.Type: GrantFiled: June 5, 1995Date of Patent: February 10, 1998Assignee: International Business Machines CorporationInventors: Thomas Norman Barker, Clive Allan Collins, Michael Charles Dapp, James Warren Dieffenderfer, Donald George Grice, Peter Michael Kogge, David Christopher Kuchinski, Billy Jack Knowles, Donald Michael Lesmeister, Richard Ernest Miles, Richard Edward Nier, Eric Eugene Retter, Robert Reist Richardson, David Bruce Rolfe, Nicholas Jerome Schoonover, Vincent John Smoral, James Robert Stupp, Paul Amba Wilkinson
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Patent number: 5710935Abstract: A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.Type: GrantFiled: June 6, 1995Date of Patent: January 20, 1998Assignee: International Business Machines CorporationInventors: Thomas Norman Barker, Clive Allan Collins, Michael Charles Dapp, James Warren Dieffenderfer, Donald George Grice, Peter Michael Kogge, David Christopher Kuchinski, Billy Jack Knowles, Donald Michael Lesmeister, Richard Ernest Miles, Richard Edward Nier, Eric Eugene Retter, Robert Reist Richardson, David Bruce Rolfe, Nicholas Jerome Schoonover, Vincent John Smoral, James Robert Stupp, Paul Amba Wilkinson