Patents by Inventor Vincent K. Chan
Vincent K. Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8847383Abstract: An integrated circuit package strip employs a stiffener layer that houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.Type: GrantFiled: February 1, 2012Date of Patent: September 30, 2014Assignee: ATI Technologies ULCInventors: Neil R. McLellan, Vincent K. Chan, Roden R. Topacio, III
-
Patent number: 8637391Abstract: A method of manufacturing a semiconductor chip is disclosed. A die having a plurality of die-pads is attached to a substrate in a semiconductor package which includes a plurality of substrate-pads. The method involves forming conductive column bumps of differing volumes extending from the die-pads; attaching each of the column bumps to a corresponding substrate-pad to form a subassembly; and reflowing the subassembly so that the column bumps form robust electrical and mechanical connections between the die pads and the substrate pads.Type: GrantFiled: May 7, 2009Date of Patent: January 28, 2014Assignee: ATI Technologies ULCInventor: Vincent K. Chan
-
Publication number: 20120127689Abstract: The present disclosure relates to an improved integrated circuit package and method with a encapsulant retention structure located adjacent to a packaged integrated chip on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the packaged integrated chip. The retention wall placed on the substrate alternatively serves as substrate stiffener able to maintain mechanical properties to be used with a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener layer of an integrated circuit package houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.Type: ApplicationFiled: February 1, 2012Publication date: May 24, 2012Applicant: ATI TECHNOLOGIES ULCInventors: Neil R. McLellan, Vincent K. Chan, Roden R. Topacio
-
Patent number: 8120170Abstract: An integrated circuit package employs a stiffener layer that houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.Type: GrantFiled: April 28, 2008Date of Patent: February 21, 2012Assignee: ATI Technologies ULCInventors: Neil R. McLellan, Vincent K. Chan, Roden R. Topacio
-
Patent number: 7985621Abstract: A method of packaging a plurality of semiconductor chips comprises: providing a substrate panel having a first coefficient of thermal expansion (CTE); providing a carrier having a second CTE that is less than the first CTE; heating the substrate panel and the carrier to first and second elevated temperatures respectively; mounting the substrate panel at about the first elevated temperature to the carrier, the carrier being at said second elevated temperature, to provide a connection between the carrier and the substrate panel; and cooling the carrier and the substrate panel from the first and second elevated temperatures thereby putting the substrate panel into tension in at least one direction. A stiffener panel may be affixed to the substrate panel and heated to an elevated temperature and while the substrate panel is heated to an elevated temperature. A plurality of dies may be mounted and electrically connected to the substrate panel.Type: GrantFiled: August 31, 2006Date of Patent: July 26, 2011Assignee: ATI Technologies ULCInventors: Vincent K. Chan, Neil McLellan, Roden Topacio
-
Publication number: 20090218689Abstract: A method of manufacturing a semiconductor chip is disclosed. A die having a plurality of die-pads is attached to a substrate in a semiconductor package which includes a plurality of substrate-pads. The method involves forming conductive column bumps of differing volumes extending from the die-pads; attaching each of the column bumps to a corresponding substrate-pad to form a subassembly; and reflowing the subassembly so that the column bumps form robust electrical and mechanical connections between the die pads and the substrate pads.Type: ApplicationFiled: May 7, 2009Publication date: September 3, 2009Applicant: ATI Technologies ULCInventor: Vincent K. CHAN
-
Patent number: 7432825Abstract: A radio frequency identification system includes an interrogator for generating and transmitting an interrogation signal to a transponder. One or more transponders of the system receive the interrogation signal and return a data signal which includes identification and/or body characteristic information in one of multiple formats. The interrogator receives the data signal, determines the format of the data signal, and decodes the data signal to obtain the identification and/or body characteristic information. The interrogator operates to decode data signals from transponders not capable of transmitting body characteristic information and transponders which are-capable of transmitting body characteristic information.Type: GrantFiled: August 4, 2003Date of Patent: October 7, 2008Assignee: Destron Fearing CorporationInventors: Vincent K. Chan, Ezequiel Mejia
-
Publication number: 20080197477Abstract: The present disclosure relates to an improved integrated circuit package with a encapsulant retention structure located adjacent to a packaged integrated chip on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the packaged integrated chip. The retention wall placed on the substrate alternatively serves as substrate stiffener able to maintain mechanical properties to be used with a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener layer of an integrated circuit package houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.Type: ApplicationFiled: April 28, 2008Publication date: August 21, 2008Applicant: ATI Technologies Inc.Inventors: Neil R. McLellan, Vincent K. Chan, Roden R. Topacio
-
Publication number: 20080169555Abstract: An integrated circuit product includes a die and an insulation layer. The insulation layer is operatively coupled to the die. The insulation layer includes a plurality of bump apertures. The insulation layer also includes an underfill anchor structure. Methods for making such an integrated circuit product are also described.Type: ApplicationFiled: January 16, 2007Publication date: July 17, 2008Applicant: ATI Technologies ULCInventors: Roden R. Topacio, Vincent K. Chan
-
Publication number: 20080057625Abstract: A method of packaging a plurality of semiconductor chips comprises: providing a substrate panel having a first coefficient of thermal expansion (CTE); providing a carrier having a second CTE that is less than the first CTE; heating the substrate panel and the carrier to first and second elevated temperatures respectively; mounting the substrate panel at about the first elevated temperature to the carrier, the carrier being at said second elevated temperature, to provide a connection between the carrier and the substrate panel; and cooling the carrier and the substrate panel from the first and second elevated temperatures thereby putting the substrate panel into tension in at least one direction. A stiffener panel may be affixed to the substrate panel and heated to an elevated temperature and while the substrate panel is heated to an elevated temperature. A plurality of dies may be mounted and electrically connected to the substrate panel.Type: ApplicationFiled: August 31, 2006Publication date: March 6, 2008Applicant: ATI Technologies Inc.Inventors: Vincent K. Chan, Neil McLellan, Roden Topacio
-
Publication number: 20080054490Abstract: The present disclosure relates to an improved integrated circuit package with a encapsulant retention structure located adjacent to a packaged integrated chip on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the packaged integrated chip. The retention wall placed on the substrate alternatively serves as substrate stiffener able to maintain mechanical properties to be used with a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener layer of an integrated circuit package houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.Type: ApplicationFiled: August 31, 2006Publication date: March 6, 2008Applicant: ATI Technologies Inc.Inventors: Neil R. McLellan, Vincent K. Chan, Roden R. Topacio
-
Publication number: 20080048321Abstract: A method of manufacturing a semiconductor chip is disclosed. A die having a plurality of die-pads is attached to a substrate in a semiconductor package which includes a plurality of substrate-pads. The method involves forming conductive column bumps of differing volumes extending from the die-pads; attaching each of the column bumps to a corresponding substrate-pad to form a subassembly; and reflowing the subassembly so that the column bumps form robust electrical and mechanical connections between the die pads and the substrate pads.Type: ApplicationFiled: August 24, 2006Publication date: February 28, 2008Applicant: ATI Technologies Inc.Inventor: Vincent K. Chan
-
Patent number: 7015826Abstract: A passive transponder including an integrated sensor is disclosed. The transponder receives an interrogation signal from a scanner, and is operable to transmit identification information and body characteristic information to a scanner. The scanner is operable to receive the identification and body characteristic information and display and/or store the information. The sensor is integrated into the transponder. If temperature is to be sensed, the transponder determines the temperature of the host using the temperature dependent characteristics of the P-N junction of the integrated circuit.Type: GrantFiled: April 2, 2002Date of Patent: March 21, 2006Assignee: Digital Angel CorporationInventors: Vincent K. Chan, Ezequiel Mejia
-
Patent number: 6849940Abstract: An integrated circuit package includes a first or active substrate and a second or passive substrate. The active substrate includes at least one circuit that generates heat during circuit operation. The passive substrate does not include any heat-generating circuits, although the passive substrate may include passive, disabled or dormant circuitry. The two substrates are preferably fabricated of semiconductor material and have substantially equal coefficients of thermal expansion. The passive substrate is thermally coupled to the active substrate preferably using a thin layer of adhesive, such as an epoxy. The passive substrate serves to thermally conduct the heat generated by the circuits of the active substrate away from the active substrate. An internal metallic heat sink may be optionally thermally coupled to the passive substrate to further aid in the transfer of heat away from the active substrate.Type: GrantFiled: November 20, 2000Date of Patent: February 1, 2005Assignee: ATI Technologies, Inc.Inventors: Vincent K. Chan, Samuel W. Ho
-
Patent number: 6798667Abstract: A solder ball collapse control apparatus and method thereof includes a plurality of first solder members, pieces of solder material in a shape capable of being used to properly create a solder joint. The first solder members have a first solder dimension and a first melting temperature and are disposed on a carrier substrate, wherein the first solder members include any piece of material capable of being disposed using a solder dispensing machine. The apparatus and method further includes a plurality of second members having a second dimension and a second melting temperature, disposed on the carrier substrate in relation to the plurality of first solder members. The second members include any piece of material capable of being disposed using the solder dispensing machine, wherein the first solder member dimension is greater than the second member dimension and the second melting temperature is greater than the first melting temperature.Type: GrantFiled: August 23, 2002Date of Patent: September 28, 2004Assignee: ATI Technologies, Inc.Inventor: Vincent K. Chan
-
Publication number: 20040036626Abstract: A radio frequency identification system includes an interrogator for generating and transmitting an interrogation signal to a transponder. One or more transponders of the system receive the interrogation signal and return a data signal which includes identification and/or body characteristic information in one of multiple formats. The interrogator receives the data signal, determines the format of the data signal, and decodes the data signal to obtain the identification and/or body characteristic information. The interrogator operates to decode data signals from transponders not capable of transmitting body characteristic information and transponders which are-capable of transmitting body characteristic information.Type: ApplicationFiled: August 4, 2003Publication date: February 26, 2004Inventors: Vincent K. Chan, Ezequiel Mejia
-
Publication number: 20040037060Abstract: A solder ball collapse control apparatus and method thereof includes a plurality of first solder members, pieces of solder material in a shape capable of being used to properly create a solder joint. The first solder members have a first solder dimension and a first melting temperature and are disposed on a carrier substrate, wherein the first solder members include any piece of material capable of being disposed using a solder dispensing machine. The apparatus and method further includes a plurality of second members having a second dimension and a second melting temperature, disposed on the carrier substrate in relation to the plurality of first solder members. The second members include any piece of material capable of being disposed using the solder dispensing machine, wherein the first solder member dimension is greater than the second member dimension and the second melting temperature is greater than the first melting temperature.Type: ApplicationFiled: August 23, 2002Publication date: February 26, 2004Applicant: ATI Technologies, Inc.Inventor: Vincent K. Chan
-
Publication number: 20030089998Abstract: A multi-chip module as disclosed herein includes a first semiconductor device, a second semiconductor device and a plurality of device interconnect members. The first semiconductor device is capable of enabling functionality associated with a first circuit segment of an integrated circuit design and includes an array of first device interconnect pads. The second semiconductor device is capable of enabling functionality associated with a second circuit segment of the integrated circuit design and includes an array of second device interconnect pads. Each one of the device interconnect members is electrically connected directly between one of the first device interconnect pads and a corresponding one of the second device interconnect pads.Type: ApplicationFiled: November 9, 2001Publication date: May 15, 2003Inventors: Vincent K. Chan, Sam Ho, Chi-Shung David Wang, Gregory C. Buchner