Abstract: In one embodiment the present invention includes a DC to DC converter device which includes an electronic circuit. The electronic circuit comprises a first comparator, a second comparator, a first switch, a first latch, and a current sensor. The inductor current includes a peak current value and a valley current value. The first comparator detects the peak current value and resets the first latch which opens the first switch. The second comparator detects the valley current value and sets the first latch which closes the first switch. The current sensor is coupled to sense an inductor current flowing through an output load, and is coupled to provide a sense voltage to the first and second comparators. In this manner, the electronic circuit provides DC to DC conversion with current control.

Abstract: In one embodiment the present invention includes a DC to DC converter device which includes an electronic circuit. The electronic circuit comprises a first comparator, a second comparator, a first switch, a first latch, and a current sensor. The inductor current includes a peak current value and a valley current value. The first comparator detects the peak current value and resets the first latch which opens the first switch. The second comparator detects the valley current value and sets the first latch which closes the first switch. The current sensor is coupled to sense an inductor current flowing through an output load, and is coupled to provide a sense voltage to the first and second comparators. In this manner, the electronic circuit provides DC to DC conversion with current control.

Abstract: In one embodiment the present invention includes a DC to DC converter device which includes an electronic circuit. The electronic circuit comprises a first comparator, a second comparator, a first switch, a first latch, and a current sensor. The inductor current includes a peak current value and a valley current value. The first comparator detects the peak current value and resets the first latch which opens the first switch. The second comparator detects the valley current value and sets the first latch which closes the first switch. The current sensor is coupled to sense an inductor current flowing through an output load, and is coupled to provide a sense voltage to the first and second comparators. In this manner, the electronic circuit provides DC to DC conversion with current control.

Abstract: In one embodiment, the present invention includes an electronic circuit for providing a power current to an LED lamp. The electronic circuit comprises a logic drive circuit, a VCO, a power switch, and a first current sensor. The VCO is coupled to provide a first logic control signal to the logic drive circuit. The power switch has a first terminal and second terminal coupled to deliver the power current to the LED lamp and a control terminal coupled to receive a power control signal from the logic drive circuit. The first current sensor is coupled to sense a peak current passing through the power switch and coupled to provide a second logic control signal to the logic drive circuit.

Abstract: In one embodiment, the present invention includes an electronic circuit for providing a power current to an LED lamp. The electronic circuit comprises a logic drive circuit, a VCO, a power switch, and a first current sensor. The VCO is coupled to provide a first logic control signal to the logic drive circuit. The power switch has a first terminal and second terminal coupled to deliver the power current to the LED lamp and a control terminal coupled to receive a power control signal from the logic drive circuit. The first current sensor is coupled to sense a peak current passing through the power switch and coupled to provide a second logic control signal to the logic drive circuit.

Abstract: In one embodiment the present invention includes a DC to DC converter device which includes an electronic circuit. The electronic circuit comprises a first comparator, a second comparator, a first switch, a first latch, and a current sensor. The inductor current includes a peak current value and a valley current value. The first comparator detects the peak current value and resets the first latch which opens the first switch. The second comparator detects the valley current value and sets the first latch which closes the first switch. The current sensor is coupled to sense an inductor current flowing through an output load, and is coupled to provide a sense voltage to the first and second comparators. In this manner, the electronic circuit provides DC to DC conversion with current control.

Abstract: A flash memory system and method for providing an array of erased flash memory cells having a reduced dispersion of erased threshold voltages. The cells of the system are erased in bulk, preferably utilizing some form of cold electron injection, and the cells are tested to determine whether the erased threshold voltage falls between a predetermined target maximum threshold voltage and a predetermined target minimum threshold voltage. In the event one or more cells has been over erased so that the measured threshold voltage is less than the target minimum values, all of the cells are lightly programmed so as to increase the actual threshold voltage. The light programming is repeated until all of the cells have an actual threshold voltage that exceeds the target minimum but is less than the target maximum.

Abstract: A flash memory system including an array of flash memory cells and at least one programmed reference cell and at least one erased reference cell disposed in a common integrated circuit. Memory array read operations are carried out by reading the two reference cells and the target cell of the memory array. The two reference cells produce a programmed reference output and an erased reference output which are averaged to provide a reference value to be compared with the read output of the target cell. In that the reference value is derived by on-chip programmed and erased cells, the reference value will automatically adapt to changes in the fabrication process, temperature, operating voltages and the like. Preferably, the reference cell outputs are also utilized to adaptively control the programming and erasing of the memory array cells so as to control the erased and programmed threshold voltages of the array cells.

Abstract: A transition detection circuit is provided comprising input means receiving the signal to be monitored for generating a first pulse having a first predetermined pulsewidth when a transition occurs in the signal being monitored; and output means responsive to the first pulse from the input means for generating a second pulse having a second predetermined pulsewidth which is less than the first predetermined pulsewidth. The present invention permits a large number of signals to be monitored for transition yet provide a highly precise output pulsewidth, all with a minimum of circuitry. Preferably the input means include a plurality of input channels, each channel being assigned to a different signal being monitored and each channel providing the first predetermined pulsewidth using simple, non-precision time delay circuits. The output state employs a single, high precision time delay circuit to provide the second predetermined pulsewidth.

Abstract: A circuit for detecting the transition of the state of logic signals at a plurality of input terminals is provided. The circuit has a transition detecting block connected to each input terminal which generates a pulse at the transition of a logic signal at the input terminal, an OR logic block connected to each transition detecting block for generating a combined logic signal from the transition detecting blocks, and a latch having SET and RESET input nodes and an output node. The SET input node is connected to the OR logic block so that the output node switches into a first logic state from a second logic state responsive to the combined logic signal on the SET input node. The circuit also has a delay unit connected to the OR logic block and to the RESET input node of the latch which precisely delays the combined logic signal to the RESET input node so that the output node of the latch switches back to the second logic state.

Abstract: A sense amplifier which is tolerant under differences in layout orientation, power supply variations and process variations is presented. The sense amplifier, operates between first and second power supplies and has two MOS transistors, each of which has a drain effectively connected to its gate to operate as functional diodes, connected in series between the first and second power supplies. The input terminal of the amplifier is connected to a node in series between the two MOS transistors and an inverter has its input node connected to the series node. The inverter's output node is coupled to the output terminal of the sense amplifier. The inverter, being responsive to a voltage at the input node, is set into one of two logic states so that a current at the sense amplifier's input terminal determines a logic state at the output terminal.

Abstract: An MOS oscillator circuit which is relatively immune to power variations in the supply is presented. A capacitor is charged and discharged in responsive to the feedback signal from a Schmitt trigger circuit. The current to charge and discharge the capacitor is generated by a current mirror which is regulated by a constant voltage generator for immunity from power supply variations.

Abstract: An output buffer circuit, which reduces its switching speed in response to the operation of a neighboring output buffer circuit, is presented. The output buffer circuit has a pair of drive transistors which switch complementarily in responsive to an input signal to the buffer circuit. In normal operation, each of the drive transistors is driven by a speed-up block for high-speed switching. When a similar drive transistor of a neighboring output buffer circuit is also switching, the speed-up block is switched off so that the drive transistor of the first output buffer circuit switches in a slower mode to avoid noise generation. The noise reduction connection between output buffer circuits is in the form of a daisy chain.

Abstract: The present invention provides protection against the effects of overerasure while essentially maintaining a single transistor per memory cell through the use of an additional transistor for each row of memory cells. The added transistor is a positive voltage threshold device which is coupled between the connected sources of the floating gate transistors and a read input line to limit the threshold voltage. For programming, a second transistor with a negative voltage threshold is coupled in the same manner, but is coupled to a program input line. The positive threshold transistor prevents an unselected transistor from turning on during a read operation.