Patents by Inventor Vincent LE Goascoz

Vincent LE Goascoz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7280003
    Abstract: A signal modulation device comprises a delta-sigma modulator disposed for transforming an amplitude-modulation signal in baseband into a pulse signal. It also comprises a phase modulator receiving, at its input, analogue phase-modulation signals in baseband. The pulse signal is mixed with carrier signals upstream of the phase modulator. The modulation device is designed to form an input stage of a transmitter.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: October 9, 2007
    Assignee: STMicroelectronics SA
    Inventors: Didier Belot, Vincent Le Goascoz, Denis Pache, Corinne Berland, Jean-François Bercher, Isabelle Hibon, Martine Villegas
  • Patent number: 7029991
    Abstract: The invention concerns a method comprising: 1) a first phase including steps which consist in forming in the upper part of a first initial semiconductor substrate a first layer of insulating material above a sectional plane of said first substrate, contacting the first layer of insulating material with the insulating upper part of a second initial substrate, so as to form a single layer of insulating material, a break at the sectional plane, so as to obtain an intermediate semiconductor substrate on the single insulating material layer; then, 2) in a second phase which consists in forming in the intermediate semiconductor substrate an additional insulating material layer adjacent to the single insulating material and topped with an upper layer of a final semiconductor substrate.
    Type: Grant
    Filed: June 21, 2001
    Date of Patent: April 18, 2006
    Assignee: STMicroelectronics S.A.
    Inventors: Vincent Le Goascoz, Herve Jaouen
  • Publication number: 20040029325
    Abstract: The invention concerns a method comprising: 1) a first phase including steps which consist in forming in the upper part of a first initial semiconductor substrate a first layer of insulating material above a sectional plane of said first substrate, contacting the first layer of insulating material with the insulating upper part of a second initial substrate, so as to form a single layer of insulating material, a break at the sectional plane, so as to obtain an intermediate semiconductor substrate on the single insulating material layer; then, 2) in a second phase which consists in forming in the intermediate semiconductor substrate an additional insulating material layer adjacent to the single insulating material and topped with an upper layer of a final semiconductor substrate.
    Type: Application
    Filed: August 1, 2003
    Publication date: February 12, 2004
    Inventors: Vincent Le Goascoz, Herve Jaouen
  • Patent number: 6593204
    Abstract: A method of fabricating, from a first semiconductor substrate having two parallel main surfaces, a system including an islet of a semiconductor material surrounded by an insulative material and resting on another insulative material includes forming a layer of a first insulative material, and forming on the top main surface of the first semiconductor substrate a thin semiconductor layer forming the islet of semiconductor material. The thin semiconductor layer can be selectively etched relative to the first semiconductor substrate. A layer of a second insulative material is formed on exposed surfaces of the islet of semiconductor material and the thin semiconductor layer. The method further includes removing the first semiconductor substrate.
    Type: Grant
    Filed: July 26, 2001
    Date of Patent: July 15, 2003
    Assignee: STMicroelectronics SA
    Inventors: Hervé Jaouen, Vincent Le Goascoz
  • Publication number: 20020019083
    Abstract: A method of fabricating, from a first semiconductor substrate having two parallel main surfaces, a system including an islet of a semiconductor material surrounded by an insulative material and resting on another insulative material includes forming a layer of a first insulative material, and forming on the top main surface of the first semiconductor substrate a thin semiconductor layer forming the islet of semiconductor material. The thin semiconductor layer can be selectively etched relative to the first semiconductor substrate. A layer of a second insulative material is formed on exposed surfaces of the islet of semiconductor material and the thin semiconductor layer. The method further includes removing the first semiconductor substrate.
    Type: Application
    Filed: July 26, 2001
    Publication date: February 14, 2002
    Applicant: STMicroelectronics S.A.
    Inventors: Herve Jaouen, Vincent Le Goascoz
  • Patent number: 4331486
    Abstract: The invention relates to a process and to an apparatus for treating semiconductor devices. A hydrogen plasma is created in the vicinity of the semiconductor devices and the positively polarized plasma particles are removed therefrom. A tightly sealed enclosure is provided and contains two plane, parallel electrodes polarized so as to form an anode and a cathode. Heating means are located in the vicinity of the anode.
    Type: Grant
    Filed: July 2, 1980
    Date of Patent: May 25, 1982
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Andre Chenevas-Paule, Vincent Le Goascoz, Pierre Viktorovitch
  • Patent number: 4143266
    Abstract: The method consists in fabricating an MOS transistor comprising a drain region and a source region separated from each other by a bulk region of opposite doping type relative to the first two regions, in delivering the radiation to be detected into the carrier-collection region of the MOS transistor, in leaving the bulk region at a floating potential and in collecting the drain-source current of the transistor.
    Type: Grant
    Filed: April 26, 1978
    Date of Patent: March 6, 1979
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Joseph Borel, Vincent Le Goascoz
  • Patent number: 4054864
    Abstract: In a method and a device for storing analog signals in integrated circuit elements, the memory elements are constituted by field-effect transistors having a number of layers of different dielectrics between the gate and the doped semiconductor substrate of the transistor. After discrete sampling of the analog signal has been performed at N points, the N amplitudes corresponding to the N points are stored in N transistors in the form of a threshold voltage.
    Type: Grant
    Filed: September 15, 1975
    Date of Patent: October 18, 1977
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Luc Audaire, Joseph Borel, Vincent Le Goascoz, Robert Poujois
  • Patent number: 4031380
    Abstract: In a method and a device for storing analog signals in integrated circuit elements, the memory elements are constituted by field-effect transistors having a number of layers of different dielectrics between the gate and the doped semiconductor substrate of the transistor. After discrete sampling of the analog signal has been performed at N points, the N amplitudes corresponding to the N points are stored in N transistors in the form of a threshold voltage.
    Type: Grant
    Filed: September 15, 1975
    Date of Patent: June 21, 1977
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Luc Audaire, Joseph Borel, Vincent Le Goascoz, Robert Poujois
  • Patent number: 3956624
    Abstract: In a method and a device for multiplying analog signals in integrated circuit elements, the memory elements are constituted by field-effect transistors having a number of layers of different dielectrics between the gate and the doped semiconductor substrate of the transistor. After discrete sampling of the analog signal has been performed at N points, the N amplitudes corresponding to the N points are stored in N transistors in the form of a threshold voltage. A multiplication of two corresponding terms is performed by recording the signal which is proportional to one sample of a function in the memory of the multiple dielectric layer type and by applying a given voltage to the gate of the transistor so as to generate a signal which is a linear function of the threshold voltage which is in turn a linear function of the writing signal at the input of a multiplier circuit.
    Type: Grant
    Filed: April 29, 1974
    Date of Patent: May 11, 1976
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Luc Audaire, Joseph Borel, Vincent LE Goascoz, Robert Poujois