Abstract: A memory circuit for storing parsimonious data and intended to receive an input vector of size Iz, includes an encoder, a memory block comprising a first memory region and a second memory region divided into a number Iz of FIFO memories, each FIFO memory being associated with one component of the input vector, only non-zero data being saved in the FIFO memories, a decoder, the encoder being configured to generate an indicator of non-zero data for each component of the input vector, the memory circuit being configured to write the non-zero data of the input data vector to the respective FIFO memories and to write the indicator of non-zero data to the first memory region, the decoder being configured to read the outputs of the FIFO memories and the associated indicator in the first memory region.

Abstract: A method is provided for optimizing the operation of a calculator implementing a neural network, the method comprising providing a neural network, providing training data relating to the values taken by the neural network parameters during a training of the neural network on a test database, determining, depending on the training data, an implementation of the neural network on hardware blocks of a calculator so as to optimize a cost relating to the operation of said the calculator implementing the neural network, the implementation being determined by decomposing the values of the neural network parameters into sub-values and by assigning to every sub-value, one hardware block from a set of hardware blocks of the calculator, and the operation of the calculator with the determined implementation.

Abstract: A memory circuit for storing parsimonious data and intended to receive an input vector of size lz, includes an encoder, a memory block comprising a first memory region and a second memory region divided into a number lz of FIFO memories, each FIFO memory being associated with one component of the input vector, only non-zero data being saved in the FIFO memories, a decoder, the encoder being configured to generate an indicator of non-zero data for each component of the input vector, the memory circuit being configured to write the non-zero data of the input data vector to the respective FIFO memories and to write the indicator of non-zero data to the first memory region, the decoder being configured to read the outputs of the FIFO memories and the associated indicator in the first memory region.

Abstract: A computer-implemented method for coding a digital signal intended to be processed by a digital computing system includes the steps of: receiving a sample of the digital signal quantized on a number Nd of bits, decomposing the sample into a plurality of binary words of parameterizable bit size Np, coding the sample through a plurality of pairs of values, each pair comprising one of the binary words and an address corresponding to the position of the binary word in the sample, transmitting the pairs of values to an integration unit in order to carry out a MAC operation between the sample and a weighting coefficient.

Abstract: A computer-implemented method is provided for coding a digital signal quantized on a given number Nd of bits and intended to be processed by a digital computing system, the signal being coded on a predetermined number Np of bits which is strictly less than Nd, the method including the steps of: receiving a digital signal composed of a plurality of samples, decomposing each sample into a sum of k maximum values which are equal to 2NP?1 and a residual value, with k being a positive or zero integer, successively transmitting the values obtained after decomposition to an integration unit for carrying out a MAC operation between the sample and a weighting coefficient.

Abstract: A processor for computing at least one convolution layer of a convolutional neural network is provided, in response to an input event, the convolutional neural network comprising at least one convolution kernel, the convolution kernel containing weight coefficients. The processor comprises at least one convolution module configured to compute the one or more convolution layers, each convolution module comprising a set of elementary processing units for computing the internal value of the convolution-layer neurons that are triggered by the input event, each convolution module being configured to match the weight coefficients of the kernel with certain at least of the elementary processing units of the module in parallel, the number of elementary processing units being independent of the number of neurons of the convolution layer.

Abstract: A device for distributing the convolution coefficients of the least one convolutional kernel of a convolutional neural network is provided, the coefficients being carried by an input bus, to a set of processing units in a processor based on a convolutional-neural-network architecture. The device comprises at least one switching network that is controlled by at least one control unit, the switching network comprising a set of switches that are arranged to apply circular shifts to at least one portion of the input bus. For each convolution kernel, each control unit is configured to dynamically control certain at least of the switches of the switching networks in response to an input event applied to the convolution kernel and at least one parameter representing the maximum size of the convolution kernels.

Abstract: A computer based on a spiking neural network, includes at least one maximum pooling layer. In response to an input spike received by a neuron of the maximum pooling layer, the device is configured so as to receive the address of the activated synapse. The device comprises an address comparator configured so as to compare the address of the activated synapse with a set of reference addresses. Each reference address is associated with a hardness value and with a pooling neuron. The device activates a neuron of the maximum pooling layer if the address of the activated synapse is equal to one of the reference addresses and the hardness value associated with this reference address has the highest value from among the hardness values associated with the other reference addresses of the set.

Abstract: This electronic calculator comprises a plurality of electronic calculation blocks, each of which is configured to implement one or more respective processing layers of an artificial neural network. The calculation blocks are of at least two different types among: a first type with fixed topology, fixed operation, and fixed parameters, a second type with fixed topology, fixed operation, and modifiable parameters, and a third type with modifiable topology, modifiable operation, and modifiable parameters. For each processing layer implemented by the respective calculation block, the topology is a connection topology for each artificial neuron; the operation is a type of processing to be performed for each artificial neuron; and the parameters include values able to be determined via training of the neural network.

Abstract: A shift-and-add multiplier able to perform multiplication operations by multiplicative values, configured to receive as input a binary value and to deliver the product of the value and of a respective multiplicative value. It includes a set of shift units, each connected to the input and configured to perform a bit shift of the value received at the input, varying from one shift unit to another; and a set of summation units, configured to sum the outputs of the shift units. It includes a set of multiplexing unit(s) connected between the set of shift units and the set of summation unit(s), and a control unit configured to control the set of multiplexing unit(s) to select respective outputs of the shift units according to the multiplicative value and to deliver them to the set of summation unit(s).

Abstract: A computer for computing a convolutional layer of an artificial neural network, includes at least one set of at least two partial sum computing modules connected in series, a storage member for storing the coefficients of at least one convolution filter, each partial sum computing module comprising at least one computing unit configured so as to carry out a multiplication of an item of input data of the computer and a coefficient of a convolution filter, followed by an addition of the output of the preceding partial sum computing module in the series, each set furthermore comprising, for each partial sum computing module except the first in the series, a shift register connected at input for storing the item of input data for the processing duration of the preceding partial sum computing modules in the series.

Abstract: A processor for computing at least one convolution layer of a convolutional neural network is provided, in response to an input event, the convolutional neural network comprising at least one convolution kernel, the convolution kernel containing weight coefficients. The processor comprises at least one convolution module configured to compute the one or more convolution layers, each convolution module comprising a set of elementary processing units for computing the internal value of the convolution-layer neurons that are triggered by the input event, each convolution module being configured to match the weight coefficients of the kernel with certain at least of the elementary processing units of the module in parallel, the number of elementary processing units being independent of the number of neurons of the convolution layer.

Abstract: A computer based on a spiking neural network, includes at least one maximum pooling layer. In response to an input spike received by a neuron of the maximum pooling layer, the device is configured so as to receive the address of the activated synapse. The device comprises an address comparator configured so as to compare the address of the activated synapse with a set of reference addresses. Each reference address is associated with a hardness value and with a pooling neuron. The device activates a neuron of the maximum pooling layer if the address of the activated synapse is equal to one of the reference addresses and the hardness value associated with this reference address has the highest value from among the hardness values associated with the other reference addresses of the set.

Abstract: A device for distributing the convolution coefficients of the least one convolutional kernel of a convolutional neural network is provided, the coefficients being carried by an input bus, to a set of processing units in a processor based on a convolutional-neural-network architecture. The device comprises at least one switching network that is controlled by at least one control unit, the switching network comprising a set of switches that are arranged to apply circular shifts to at least one portion of the input bus. For each convolution kernel, each control unit is configured to dynamically control certain at least of the switches of the switching networks in response to an input event applied to the convolution kernel and at least one parameter representing the maximum size of the convolution kernels.