Patents by Inventor Vincent M. Rogers

Vincent M. Rogers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Adding test access to a back-drilled VIA
    Patent number: 9894773
    Abstract: Embodiments of the invention relates to adding test access to a back-drilled vertical access interconnect (VIA) of a printed circuit board (PCB). A VIA is either formed or provided as an opening through layers of the PCB. The VIA is countersunk from one of the two openings to the PCB prior to plating to form a surface that can be used as a test target. The countersunk VIA is subject to plating so that the interior walls and surfaces of the VIA are covered with a conductive material. The plating is removed along the walls of the countersunk section of the VIA, so that the plating remains on the shoulders and the non-countersunk section of the VIA with the shoulder in communication with a trace internal to the PCB. The back-drilled VIA with the plating configuration provides an internal conducting surface for contact while mitigating interference associated with a VIA stub.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: February 13, 2018
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Derek Robertson, Vincent M. Rogers
  • ADDING TEST ACCESS TO A BACK-DRILLED VIA
    Publication number: 20150173201
    Abstract: Embodiments of the invention relates to adding test access to a back-drilled vertical access interconnect (VIA) of a printed circuit board (PCB). A VIA is either formed or provided as an opening through layers of the PCB. The VIA is countersunk from one of the two openings to the PCB prior to plating to form a surface that can be used as a test target. The countersunk VIA is subject to plating so that the interior walls and surfaces of the VIA are covered with a conductive material. The plating is removed along the walls of the countersunk section of the VIA, so that the plating remains on the shoulders and the non-countersunk section of the VIA with the shoulder in communication with a trace internal to the PCB. The back-drilled VIA with the plating configuration provides an internal conducting surface for contact while mitigating interference associated with a VIA stub.
    Type: Application
    Filed: December 17, 2013
    Publication date: June 18, 2015
    Applicant: International Business Machines Corporation
    Inventors: Derek Robertson, Vincent M. Rogers