Abstract: A three-dimensional coil inductor is disclosed. The inductor includes a substrate; a set of lower electrically conductive traces positioned on the substrate; a core placed over the lower traces; a set of side electrically conductive traces laid on the core and the lower traces; and a set of upper electrically conductive traces attached to the side traces so as to form the inductor. Fabrication of the inductor includes the steps of forming a set of lower traces on a substrate; positioning a core over the lower traces; forming a set of side traces on the core; connecting the side traces to the lower traces; forming a set of upper traces on the core; and connecting the upper traces to the side traces so as to form a coil structure.

Abstract: A process which vastly improves the 3-D patterning capability of laser pantography (computer controlled laser direct-write patterning). The process uses commercially available electrodeposited photoresist (EDPR) to pattern 3-D surfaces. The EDPR covers the surface of a metal layer conformally, coating the vertical as well as horizontal surfaces. A laser pantograph then patterns the EDPR, which is subsequently developed in a standard, commercially available developer, leaving patterned trench areas in the EDPR. The metal layer thereunder is now exposed in the trench areas and masked in others, and thereafter can be etched to form the desired pattern (subtractive process), or can be plated with metal (additive process), followed by a resist stripping, and removal of the remaining field metal (additive process). This improved laser pantograph process is simpler, faster, move manufacturable, and requires no micro-machining.

Abstract: An attachment method for stacked integrated circuit (IC) chips. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus.

Abstract: A manufacturable process for fabricating electrical interconnects which extend from a top surface of an integrated circuit chip to a sidewall of the chip using laser pantography to pattern three dimensional interconnects. The electrical interconnects may be of an L-connect or L-shaped type. The process implements three dimensional (3D) stacking by moving the conventional bond or interface pads on a chip to the sidewall of the chip. Implementation of the process includes: 1) holding individual chips for batch processing, 2) depositing a dielectric passivation layer on the top and sidewalls of the chips, 3) opening vias in the dielectric, 4) forming the interconnects by laser pantography, and 5) removing the chips from the holding means. The process enables low cost manufacturing of chips with bond pads on the sidewalls, which enables stacking for increased performance, reduced space, and higher functional per unit volume.

Abstract: A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets.For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder.

Abstract: A device is available for bonding one component to another, particularly for bonding electronic components of integrated circuits, such as chips, to a substrate. The bonder device in one embodiment includes a bottom metal block having a machined opening wherein a substrate is located, a template having machined openings which match solder patterns on the substrate, a thin diaphragm placed over the template after the chips have been positioned in the openings therein, and a top metal block positioned over the diaphragm and secured to the bottom block, with the diaphragm retained therebetween. The top block includes a countersink portion which extends over at least the area of the template and an opening through which a high pressure inert gas is supplied to exert uniform pressure distribution over the diaphragm to keep the chips in place during soldering. A heating means is provided to melt the solder patterns on the substrate and thereby solder the chips thereto.