Abstract: Example implementations relate to partitioning memory modules into volatile and non-volatile portions. For example, a system includes a memory controller to partition a memory module into a non-volatile portion and a volatile portion and to identify persistent data to be backed up during a power loss condition. The memory controller is further to transfer the persistent data from the volatile portion of the memory module to the non-volatile portion of the memory module, in response to the power loss condition.

Abstract: Example implementations relate to chipset reconfiguration based on device detection. For example, a method includes detecting, by a computing system, that a storage device is connected to an input/output (I/O) interface of the computing system, and reconfiguring a chipset of the computing system based on the detected storage device. The method also includes performing a power cycle on chipset standby power to trigger a chipset configuration reload.

Abstract: Acrylate-acrylamide copolymers are disclosed. They are rigid and glassy in dry state at room temperature (from about 23° C. to about 28° C.), but are soft and very deformable and have a high refractive index, a high glistening resistance and a low aging-related surface light scattering in fully hydrated state. They are particularly suitable for making wet-packed intraocular lenses (IOLs) which can be delivered through sub 2.0 mm incisions.

Abstract: Provided in one example is an article. The article including: a first electrode; a switching layer disposed over at least a portion of the first electrode, the switching layer including a metal oxide; and a second electrode disposed over at least a portion of the switching layer. The first electrode, the switching layer, and the second electrode are parts of a resistive random-access memory, and one or both of the first electrode and the second electrode is a part of a layer of a printed circuit board.

Abstract: A computing system for dynamically changing at least one input/output configuration between a motherboard of a computing device and at least one node connected to the motherboard includes a plurality of interchangeable topology transformation units (TTU) risers to connect at least one processing device located on a motherboard of the computing system to a plurality of computing nodes. Each of the TTU risers include topologies designed to support different workloads with respect to another TTU riser.

Abstract: Example implementations relate to data backup. For example, a data backup can include tracking a location of a data block on a first node and initiating a transfer, utilizing a backup power supply, of the data block to a non-volatile memory location on a second node in response to an interruption of a primary power supply. In addition, the data block can be restored to the tracked location of the first node responsive to a restoration of the primary power supply.

Abstract: During runtime of a system, a memory controller is caused to relinquish control of a memory module that includes a volatile memory and a non-volatile memory. After the triggering, an indication is activated to the memory module, the indication causing a backup operation in the memory module, the backup operation being controlled by an internal controller in the memory module, and the backup operation involving a transfer of data from the volatile memory to the non-volatile memory in the memory module.

Abstract: An example mounting assembly is provided herein. The mounting assembly includes a first cage, a second cage, a rail member, a rigid cable member, a latch member, and a lock mechanism. The rail member to move the first cage and the second cage between an installed position, an access position, and a transitional position. The rigid cable member to move with the first cage and the second cage along the rail member. The latch member to retain the first cage and the second cage in the installed position. The lock mechanism to hold the second cage in the access position.

Abstract: A system management controller with a consolidated memory is disclosed. The example computing device includes a processor to host an operating system and a system memory to be used by the processor to execute instructions. The computing device also includes a management controller to enable out-of-band management of the computing device. The management controller includes a consolidated memory device. A first memory block of the consolidated memory device is used by the management controller as a working memory and a second memory block of the consolidated memory device is used for long-term storage of programming instructions.

Abstract: To migrate data from a first storage system to a second storage system, the second storage system detects a migration of a persistent storage media from the first storage system to the second storage system. In response to detecting the migration of the persistent storage media, write information from a write cache in the first storage system is copied to a write cache in the second storage system, where the write caches in the first and second storage systems were not maintained synchronously before the write information from the write cache in the first storage system is copied to the write cache in the second storage system.

Abstract: A technique for providing backup power can include determining a backup power demand of at least two nodes on a chassis, each node supporting multiple loads. A technique for providing backup power can include selectively enabling an output of power from a battery module to the at least two nodes.

Abstract: Example techniques for using a release latch to access a second tray of a server are disclosed. An example method includes operating a server in a rack. A release latch is engaged to initiate movement of a first tray of the server away from a second tray located behind the first tray. The second tray can then be accessed to remove and replace a storage drive from the second tray while the server remains in operation.

Abstract: Example techniques for using a release latch to access a second tray of a server are disclosed. An example method includes operating a server in a rack. A release latch is engaged to initiate movement of a first tray of the server away from a second tray located behind the first tray. The second tray can then be accessed to remove and replace a storage drive from the second tray while the server remains in operation.

Abstract: Acrylate-acrylamide copolymers are disclosed. They are rigid and glassy in dry state at room temperature (from about 23° C. to about 28° C.), but are soft and very deformable and have a high refractive index, a high glistening resistance and a low aging-related surface light scattering in fully hydrated state. They are particularly suitable for making wet-packed intraocular lenses (IOLs) which can be delivered through sub 2.0 mm incisions.

Abstract: Acrylate-acrylamide copolymers are disclosed. They are rigid and glassy in dry state at room temperature (from about 23° C. to about 28° C.), but are soft and very deformable and have a high refractive index, a high glistening resistance and a low aging-related surface light scattering in fully hydrated state. They are particularly suitable for making wet-packed intraocular lenses (IOLs) which can be delivered through sub 2.0 mm incisions.

Abstract: During runtime of a system, a memory controller is caused to relinquish control of a memory module that includes a volatile memory and a non-volatile memory. After the triggering, an indication is activated to the memory module, the indication causing a backup operation in the memory module, the backup operation being controlled by an internal controller in the memory module, and the backup operation involving a transfer of data from the volatile memory to the non-volatile memory in the memory module.

Abstract: An example processor includes a plurality of processor core components, a memory interface component, and an address translation gasket. Each processor core component is assigned to one of a plurality of system images, and the plurality of system images share a common memory component by at least utilizing the address translation gasket to maintain separation between memory regions assigned to each of the plurality of system images. The memory interface component is shared by the plurality of independent system images. The address translation gasket is configured to intercept transactions bound for the memory interface component comprising a system image identifier and a target address, generate a translation address based at least in part on the system identifier and the target address, and send the translation address to the memory interface component.

Abstract: Systems and methods for flow control within a Serial Peripheral Interface without additional signal lines are included herein. In one example, a method includes generating a flow control command. The method also includes sending the flow control command from a master device to a slave device with a Serial Peripheral Interface. In addition, the method includes sending a memory address from the master device to the slave device. Furthermore, the method includes detecting a ready indicator in the master device. The method also includes waiting to receive a ready indicator and communicating with the slave device in response to the ready indicator.

Abstract: An example processor includes a plurality of processing core components, one or more memory interface components, and a management component, wherein the one or more memory interface components are each shared by the plurality of processing core components, and wherein the management component is configured to assign each of the plurality of processing core components to one of a plurality of system images.

Abstract: A multi-protocol multiplexer provides signals according to different protocols for accessing a storage subsystem to a connector, where the signals according to a first protocol are to be routed over a first subset of channels of an interconnect to the storage subsystem, and the signals according to a second protocol are routed over a second subset of channels of the interconnect.