Patents by Inventor Vincent Philippe Schuppe
Vincent Philippe Schuppe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11475200Abstract: Various implementations described herein are directed to an apparatus having a processor and memory having instructions stored thereon that, when executed by the processor, cause the processor to identify conductive paths in a physical layout of an integrated circuit having nodal features that define a connective structure of the integrated circuit. The instructions may cause the processor to traverse the conductive paths to detect valid metals and redundant metals. The valid metals may refer to valid conductive paths between the nodal features that conjoin the nodal features. The redundant metals may refer to unused conductive paths that provide disjointed paths from the nodal features. The instructions may cause the processor to indicate the valid metals as marked with a first indicator and to indicate the redundant metals as unmarked with a second indicator that is different than the first indicator.Type: GrantFiled: June 4, 2020Date of Patent: October 18, 2022Assignee: Arm LimitedInventors: Yulin Shi, Vincent Philippe Schuppe, Ettore Amirante
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Publication number: 20210383050Abstract: Various implementations described herein are directed to an apparatus having a processor and memory having instructions stored thereon that, when executed by the processor, cause the processor to identify conductive paths in a physical layout of an integrated circuit having nodal features that define a connective structure of the integrated circuit. The instructions may cause the processor to traverse the conductive paths to detect valid metals and redundant metals. The valid metals may refer to valid conductive paths between the nodal features that conjoin the nodal features. The redundant metals may refer to unused conductive paths that provide disjointed paths from the nodal features. The instructions may cause the processor to indicate the valid metals as marked with a first indicator and to indicate the redundant metals as unmarked with a second indicator that is different than the first indicator.Type: ApplicationFiled: June 4, 2020Publication date: December 9, 2021Inventors: Yulin Shi, Vincent Philippe Schuppe, Ettore Amirante
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Patent number: 10579775Abstract: Various implementations described herein are directed to a method that identifies a memory instance with multiple tile-cells. The memory instance has memory instance leakage data, and each tile-cell of the multiple tile-cells has tile-cell leakage data. The method subdivides the multiple tile-cells into multiple categories based on a relationship between the memory instance leakage data and the tile-cell leakage data. The method obtains measured leakage data for each tile-cell of the multiple tile-cells by simulating the memory instance based on the memory instance leakage data and the tile-cell leakage data for each category of the multiple categories. The method determines a combined leakage of the memory instance by combining the measured leakage data for each tile-cell of the multiple tile-cells.Type: GrantFiled: July 11, 2018Date of Patent: March 3, 2020Assignee: Arm LimitedInventors: Vincent Philippe Schuppe, Syam Kumar Lalitha Gopalakrishnan Nair, Hongwei Zhu, Neeraj Dogra, Mouli Rajaram Chollangi, Arjun R. Prasad
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Publication number: 20200019669Abstract: Various implementations described herein are directed to a method that identifies a memory instance with multiple tile-cells. The memory instance has memory instance leakage data, and each tile-cell of the multiple tile-cells has tile-cell leakage data. The method subdivides the multiple tile-cells into multiple categories based on a relationship between the memory instance leakage data and the tile-cell leakage data. The method obtains measured leakage data for each tile-cell of the multiple tile-cells by simulating the memory instance based on the memory instance leakage data and the tile-cell leakage data for each category of the multiple categories. The method determines a combined leakage of the memory instance by combining the measured leakage data for each tile-cell of the multiple tile-cells.Type: ApplicationFiled: July 11, 2018Publication date: January 16, 2020Inventors: Vincent Philippe Schuppe, Syam Kumar Lalitha Gopalakrishnan Nair, Hongwei Zhu, Neeraj Dogra, Mouli Rajaram Chollangi, Arjun R. Prasad
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Patent number: 10403643Abstract: Various implementations described herein are directed to an integrated circuit having multiple access wires including a first access wire coupled to a first access port of the integrated circuit and a second access wire coupled to a second access port of the integrated circuit. The integrated circuit may include inverter circuitry having a first plurality of inverters coupled to the first access wire and a second plurality of inverters coupled to the second access wire. The first plurality of inverters may be positioned adjacent to the second plurality of inverters in an alternating manner.Type: GrantFiled: May 4, 2017Date of Patent: September 3, 2019Assignee: ARM LimitedInventors: Yew Keong Chong, Sriram Thyagarajan, Vincent Philippe Schuppe
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Publication number: 20180323215Abstract: Various implementations described herein are directed to an integrated circuit having multiple access wires including a first access wire coupled to a first access port of the integrated circuit and a second access wire coupled to a second access port of the integrated circuit. The integrated circuit may include inverter circuitry having a first plurality of inverters coupled to the first access wire and a second plurality of inverters coupled to the second access wire. The first plurality of inverters may be positioned adjacent to the second plurality of inverters in an alternating manner.Type: ApplicationFiled: May 4, 2017Publication date: November 8, 2018Inventors: Yew Keong Chong, Sriram Thyagarajan, Vincent Philippe Schuppe
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Publication number: 20170062043Abstract: Various implementations described herein are directed to a device for dynamic capacitance balancing. The device may include a sense amplifier configured to receive complimentary data signals from complimentary bitlines and provide first and second sensed data signals based on received complimentary data signals. The second sensed data signal may be a compliment of the first sensed data signal. The device may include a balance coupler configured to receive the second sensed data signal from the sense amplifier and provide a modified second sensed data signal having capacitance similar to the first sensed data signal. The device may include a latch configured to receive the first sensed data signal from the sense amplifier, receive the modified second sensed data signal from the balance coupler, and provide a latched data signal based on the first and modified second sensed data signals.Type: ApplicationFiled: January 29, 2016Publication date: March 2, 2017Inventors: Vincent Philippe Schuppe, Sushil Kumar, Daksheshkumar Maganbhai Malaviya, Hemant Hemraj Parate
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Patent number: 9570157Abstract: Various implementations described herein are directed to a device for dynamic capacitance balancing. The device may include a sense amplifier configured to receive complimentary data signals from complimentary bitlines and provide first and second sensed data signals based on received complimentary data signals. The second sensed data signal may be a compliment of the first sensed data signal. The device may include a balance coupler configured to receive the second sensed data signal from the sense amplifier and provide a modified second sensed data signal having capacitance similar to the first sensed data signal. The device may include a latch configured to receive the first sensed data signal from the sense amplifier, receive the modified second sensed data signal from the balance coupler, and provide a latched data signal based on the first and modified second sensed data signals.Type: GrantFiled: January 29, 2016Date of Patent: February 14, 2017Assignee: ARM LimitedInventors: Vincent Philippe Schuppe, Sushil Kumar, Daksheshkumar Maganbhai Malaviya, Hemant Hemraj Parate
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Publication number: 20130308407Abstract: A semiconductor memory storage device having a plurality of storage cells for storing data, each storage cell comprising an access control device and access control circuitry. The access control circuitry is configured to respond to a data access request signal to access a selected storage cell connected to a corresponding selected access control line to: control the voltage control switching circuitry to connect the at least one capacitor to the voltage supply line such that the at least one capacitor is charged by the voltage supply line and a voltage level on the voltage supply line is reduced; and to control the access control line switching circuitry to connect the selected access control line to the voltage supply line having the reduced voltage level.Type: ApplicationFiled: May 21, 2012Publication date: November 21, 2013Applicant: ARM LIMITEDInventors: Amaranth Shyanmugam, Bikas Maiti, Vincent Philippe Schuppe, Yew Keong Chong, Martin Jay Kinkade, Hsin-Yu Chen
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Patent number: 8422262Abstract: A method of generating a ROM bit cell array layout including the steps of: inputting a predetermined memory architecture having a predetermined positioning of bit lines and virtual ground lines, the memory architecture including a plurality of columns of memory cells, each column of memory cells being located between associated bit lines and virtual ground lines. Adjacent memory cells in each column of memory cells share a common connection to either the associated bit line or the associated virtual ground line. The further steps of evaluating the width of active area of each of said columns of memory cells, in dependence on said predetermined positioning of bit lines and virtual ground lines; selecting a final width of active area in dependence on at least one performance characteristic associated with said final width of active area; and generating the layout according to said final width of active area.Type: GrantFiled: April 7, 2011Date of Patent: April 16, 2013Assignee: ARM LimitedInventors: Yannick Marc Nevers, Vincent Philippe Schuppe
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Publication number: 20110249481Abstract: A method of generating a ROM bit cell array layout is provided, the method comprising the steps of: inputting a predetermined memory architecture having a predetermined positioning of bit lines and virtual ground lines, said memory architecture comprising a plurality of columns of memory cells, each column of memory cells being located between its own associated bit line and its own associated virtual ground line, and adjacent memory cells in each column of memory cells sharing a common connection to either said associated bit line or said associated virtual ground line; evaluating a possible range of width of active area of each of said columns of memory cells, in dependence on said predetermined positioning of bit lines and virtual ground lines; selecting a final width of active area in dependence on at least one performance characteristic associated with said final width of active area; and generating said ROM bit cell array layout according to said final width of active area.Type: ApplicationFiled: April 7, 2011Publication date: October 13, 2011Applicant: ARM LimitedInventors: Yannick Marc Nevers, Vincent Philippe Schuppe
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Patent number: 7961490Abstract: A method of generating a ROM bit cell array layout is provided, the method comprising the steps of: inputting a predetermined memory architecture having a predetermined positioning of bit lines and virtual ground lines, said memory architecture comprising a plurality of columns of memory cells, each column of memory cells being located between its own associated bit line and its own associated virtual ground line, and adjacent memory cells in each column of memory cells sharing a common connection to either said associated bit line or said associated virtual ground line; evaluating a possible range of width of active area of each of said columns of memory cells, in dependence on said predetermined positioning of bit lines and virtual ground lines; selecting a final width of active area in dependence on at least one performance characteristic associated with said final width of active area; and generating said ROM bit cell array layout according to said final width of active area.Type: GrantFiled: January 9, 2009Date of Patent: June 14, 2011Assignee: ARM LimitedInventors: Yannick Marc Nevers, Vincent Philippe Schuppe
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Publication number: 20100177544Abstract: A method of generating a ROM bit cell array layout is provided, the method comprising the steps of: inputting a predetermined memory architecture having a predetermined positioning of bit lines and virtual ground lines, said memory architecture comprising a plurality of columns of memory cells, each column of memory cells being located between its own associated bit line and its own associated virtual ground line, and adjacent memory cells in each column of memory cells sharing a common connection to either said associated bit line or said associated virtual ground line; evaluating a possible range of width of active area of each of said columns of memory cells, in dependence on said predetermined positioning of bit lines and virtual ground lines; selecting a final width of active area in dependence on at least one performance characteristic associated with said final width of active area; and generating said ROM bit cell array layout according to said final width of active area.Type: ApplicationFiled: January 9, 2009Publication date: July 15, 2010Applicant: ARM LIMITEDInventors: Yannick Marc Nevers, Vincent Philippe Schuppe
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Patent number: 7613053Abstract: A memory device and method of operation are provided. The memory device comprises a plurality of memory cells arranged in at least one column, during a write operation a data value being written to an addressed memory cell within a selected column from said at least one column. A supply voltage line is associated with each column, the supply voltage line being connectable to a first voltage source to provide a supply voltage at a first voltage level to the associated column. Threshold circuitry is connected to a second voltage source having a second voltage level, the threshold circuitry having a threshold voltage. Control circuitry is used during the write operation to disconnect the supply voltage line for the selected column from the first voltage source, and to connect the threshold circuitry to the supply voltage line for the selected column.Type: GrantFiled: November 23, 2007Date of Patent: November 3, 2009Assignee: ARM LimitedInventors: Nicolaas Klarinus Johannes van Winkelhoff, Sebastien Nicolas Ricavy, Christophe Denis Lucien Frey, Denis René André Dufourt, Vincent Philippe Schuppe
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Publication number: 20090135663Abstract: A memory device and method of operation are provided. The memory device comprises a plurality of memory cells arranged in at least one column, during a write operation a data value being written to an addressed memory cell within a selected column from said at least one column. A supply voltage line is associated with each column, the supply voltage line being connectable to a first voltage source to provide a supply voltage at a first voltage level to the associated column. Threshold circuitry is connected to a second voltage source having a second voltage level, the threshold circuitry having a threshold voltage. Control circuitry is used during the write operation to disconnect the supply voltage line for the selected column from the first voltage source, and to connect the threshold circuitry to the supply voltage line for the selected column.Type: ApplicationFiled: November 23, 2007Publication date: May 28, 2009Applicant: ARM LimitedInventors: Nicolaas Klarinus Johannes van Winkelhoff, Sebastien Nicolas Ricavy, Christophe Denis Frey, Denis Rene Andre Dufourt, Vincent Philippe Schuppe