Abstract: An apparatus such as a node in a daisy chain of electronic devices includes a serial data input port receive input from an electronic device in the daisy chain. The apparatus includes a serial data output port to send output to another electronic device in the daisy chain. The apparatus includes a chip select input port configured to receive input from a master control unit, and an interface circuit configured to, in a daisy chain streaming mode, and based on a received command and changed edge of a signal on the chip select input port, repeatedly: read data from a data source of the apparatus to yield data, output the data to the serial data output port, and copy other data received at the serial data input port to the serial data output port after the data.

Abstract: An apparatus may include a serial data output port configured to send output data to a electronic device. The apparatus may include a serial data input port configured to receive input data from another electronic device. The apparatus may include a chip select output port configured to send output to the electronic devices connected in a daisy chain. The apparatus may include a interface circuit, configured to determine that a given electronic device is to selectively execute a first command. The interface circuit may be further configured to issue a complex command to the electronic devices connected. The complex command may indicate to the f electronic devices that additional commands are to be selectively executed.

Abstract: A node in a daisy chain includes a serial data input port configured to receive input from an electronic device, a serial data output port configured to send output to another electronic device, a chip select input port configured to receive input from a master control unit, a timer, and an interface circuit. The interface circuit may be configured to, in a daisy chain mode, copy data received at the serial data input port to the serial data output port, and upon receipt of a changed edge of a chip select signal on the chip select input port, initiate the timer. The interface circuit may be configured to, upon the completion of a time to be determined by the timer, enter the daisy chain mode.

Abstract: An analog to digital converter (ADC) includes voltage and reference input terminals, a buffer circuit, and control logic. The buffer circuit includes input and output terminals and a variable resistor including resistive branches connected in parallel. The control logic is configured to, in a calibration phase, determine a given gain value for which gain error is to be calibrated, determine a set of the resistive branches in the buffer circuit to be used to achieve the given gain value, successively enable a different resistive branch of the variable resistor of the set until all resistive branches of the set have been enabled, determine an output code resulting after enabling all resistive branches of the set, and, from the output code, determine a gain error of the given gain value. The control logic is further configured to take corrective action based upon the gain error of the given gain value.

Abstract: An analog to digital converter (ADC) circuit includes voltage and reference input terminals, a sample circuit, and control logic. The sample circuit includes input and output terminals, and capacitors connected in parallel and arranged between the input and output terminals. The control logic is configured to, in a calibration phase of operation, cause the multiplexer to route the ADC reference input terminal to the sampling voltage input terminal, determine a given gain value, determine a set of the capacitors to be used to achieve the given gain value, successively enable capacitor subsets to sample voltage of the reference input while disabling a remainder of the capacitors until all capacitors have been enabled, determine a resulting output code, and from the output code, determine a gain error of the given gain value of the ADC circuit.

Abstract: An apparatus may include a serial data output port configured to send output data to a electronic device. The apparatus may include a serial data input port configured to receive input data from another electronic device. The apparatus may include a chip select output port configured to send output to the electronic devices connected in a daisy chain. The apparatus may include a interface circuit, configured to determine that a given electronic device is to selectively execute a first command. The interface circuit may be further configured to issue a complex command to the electronic devices connected. The complex command may indicate to the f electronic devices that additional commands are to be selectively executed.

Abstract: An apparatus such as a node in a daisy chain of electronic devices includes a serial data input port receive input from an electronic device in the daisy chain. The apparatus includes a serial data output port to send output to another electronic device in the daisy chain. The apparatus includes a chip select input port configured to receive input from a master control unit, and an interface circuit configured to, in a daisy chain streaming mode, and based on a received command and changed edge of a signal on the chip select input port, repeatedly: read data from a data source of the apparatus to yield data, output the data to the serial data output port, and copy other data received at the serial data input port to the serial data output port after the data.

Abstract: A node in a daisy chain includes a serial data input port configured to receive input from an electronic device, a serial data output port configured to send output to another electronic device, a chip select input port configured to receive input from a master control unit, a timer, and an interface circuit. The interface circuit may be configured to, in a daisy chain mode, copy data received at the serial data input port to the serial data output port, and upon receipt of a changed edge of a chip select signal on the chip select input port, initiate the timer. The interface circuit may be configured to, upon the completion of a time to be determined by the timer, enter the daisy chain mode.

Abstract: An analog to digital converter (ADC) includes voltage and reference input terminals, a buffer circuit, and control logic. The buffer circuit includes input and output terminals and a variable resistor including resistive branches connected in parallel. The control logic is configured to, in a calibration phase, determine a given gain value for which gain error is to be calibrated, determine a set of the resistive branches in the buffer circuit to be used to achieve the given gain value, successively enable a different resistive branch of the variable resistor of the set until all resistive branches of the set have been enabled, determine an output code resulting after enabling all resistive branches of the set, and, from the output code, determine a gain error of the given gain value. The control logic is further configured to take corrective action based upon the gain error of the given gain value.

Abstract: An analog to digital converter (ADC) circuit includes voltage and reference input terminals, a sample circuit, and control logic. The sample circuit includes input and output terminals, and capacitors connected in parallel and arranged between the input and output terminals. The control logic is configured to, in a calibration phase of operation, cause the multiplexer to route the ADC reference input terminal to the sampling voltage input terminal, determine a given gain value, determine a set of the capacitors to be used to achieve the given gain value, successively enable capacitor subsets to sample voltage of the reference input while disabling a remainder of the capacitors until all capacitors have been enabled, determine a resulting output code, and from the output code, determine a gain error of the given gain value of the ADC circuit.

Abstract: A method includes receiving samples of digital to analog converter (DAC), partitioning the samples to unit-DACs based upon previous partitions of inputs to the unit-DACs to cancel out integrated non-linearities of outputs of the DAC caused by the gain mismatches of the unit-DACs, including partitioning samples of DAC input to the unit-DACs through a recursive nth order partitioning algorithm. The algorithm includes, for each DAC input, determining a first partition of the DAC input that would cancel an (n?1)th order previously integrated non-linearity, adding an equivalent DAC input of the first partition to the DAC input to obtain a total DAC input, using a first order application of the total DAC input to the inputs of the unit-DACs to yield a second partition of DAC input, summing the first and second partitions generate a final partition, and, based on the final partition, computing non-linearity remainders at each order of integration.

Abstract: A charge transfer digital-to-analog converter includes a differential reference voltage, a pair of capacitors, and switches including a shorting switch. The switches are configured to be switched in successive phases to generate a charge transfer through the capacitors to generate an output corresponding to a digital input. The specific switches activated and deactivated in each phase are selected according to the digital input. Each capacitor of the pair of capacitors is connected to a respective pin for the output. The shorting switch is configured to short the pair of capacitors to create a zero-differential charge on a first side of the capacitors. The shorting switch is implemented with a bootstrap circuit to maintain a constant common mode voltage of the first side of the capacitors while the shorting switch is activated.

Abstract: A charge transfer digital-to-analog converter includes a differential reference voltage, a pair of capacitors, and switches including a shorting switch. The switches are configured to be switched in successive phases to generate a charge transfer through the capacitors to generate an output corresponding to a digital input. The specific switches activated and deactivated in each phase are selected according to the digital input. Each capacitor of the pair of capacitors is connected to a respective pin for the output. The shorting switch is configured to short the pair of capacitors to create a zero-differential charge on a first side of the capacitors. The shorting switch is implemented with a bootstrap circuit to maintain a constant common mode voltage of the first side of the capacitors while the shorting switch is activated.

Abstract: A power metering circuit includes a current input path for receiving an analog current input at a first analog to digital converter; a voltage input path for receiving an analog voltage input at a second analog to digital converter; a multiplier configured to multiply an output of the current input path and the voltage input path; a notch filter configured to receive an output of the multiplier, the notch filter having a stop band based on a line frequency; and a control circuit for setting a sampling frequency of the first analog to digital converter and the second analog to digital converter to a multiple of the line frequency.

Abstract: A sigma-delta analog to digital converter (ADC) includes an M-bit digital-to-analog converter (DAC); a loop filter coupled to receive an output from DAC; and a variable level quantizer configured to provide a uniform quantization function by switching between an N-level quantizer function and an N?1 level quantizer function.

Abstract: An analog-to-digital converter includes circuitry for receiving an analog input and converting the input to a digital signal; and non-transitory control circuitry configured for: receiving a sampling time; receiving a conversion time; determining a power up time from at least one sleep mode; and causing the digital-to-analog converter to enter into the at least one sleep mode if the sum of the power up time and conversion time is less than the sampling time

Abstract: An analog-to-digital converter includes circuitry for receiving an analog input and converting the input to a digital signal; and non-transitory control circuitry configured for: receiving a sampling time; receiving a conversion time; determining a power up time from at least one sleep mode; and causing the digital-to-analog converter to enter into the at least one sleep mode if the sum of the power up time and conversion time is less than the sampling time.

Abstract: A power metering circuit includes a current input path for receiving an analog current input at a first analog to digital converter; a voltage input path for receiving an analog voltage input at a second analog to digital converter; a multiplier configured to multiply an output of the current input path and the voltage input path; a notch filter configured to receive an output of the multiplier, the notch filter having a stop band based on a line frequency; and a control circuit for setting a sampling frequency of the first analog to digital converter and the second analog to digital converter to a multiple of the line frequency.

Abstract: A sigma-delta analog to digital converter (ADC) includes an M-bit digital-to-analog converter (DAC); a loop filter coupled to receive an output from DAC; and a variable level quantizer configured to provide a uniform quantization function by switching between an N-level quantizer function and an N-1 level quantizer function

Abstract: An input stage for a switched capacitor analog-to-digital converter has a differential voltage input receiving an input voltage, a differential reference voltage input receiving a chopped reference voltage, a common voltage connection, and a differential output. A pair of input capacitors is coupled between the differential voltage input and the differential output and a pair of reference capacitors is coupled between the differential reference voltage input. A switching unit is controlled by a first and second phase operable during the first phase to connect a first terminal of the input capacitors with the common voltage connection and couple the first terminal of the reference capacitors with the inverted differential voltage reference; and during a second phase to connect the first terminal of the input capacitors with the differential input voltage and couple the first terminal of the reference capacitors with the non-inverted differential voltage reference.