Patents by Inventor Vincent R. Freytag

Vincent R. Freytag has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory mirroring and migration at home agent
    Patent number: 8799586
    Abstract: Methods and apparatus relating to memory mirroring and migration at a Home Agent (HA) are described. In one embodiment, a home agent may mirror its data at a slave agent. In some embodiments, a bit in a directory may indicate status of cache lines. Other embodiments are also disclosed.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: August 5, 2014
    Assignee: Intel Corporation
    Inventors: Ganesh Kumar, Dheemanth Nagaraj, Vincent R. Freytag, Eric Delano, Gregory S. Averill
  • Controllably exiting an unknown state of a cache coherency directory
    Patent number: 8782347
    Abstract: In one embodiment, a method includes receiving a read request from a first caching agent and if a directory entry associated with the request is in an unknown state, an invalidating snoop message is sent to at least one other caching agent to invalidate information in a cache location of the other caching agent corresponding to the location of the read request, to enable setting of the directory entry into a known state. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: July 15, 2014
    Assignee: Intel Corporation
    Inventors: Ganesh Kumar, Dheemanth Nagaraj, Vincent R. Freytag, Eric DeLano, Gregory S. Averill
  • Home agent data and memory management
    Patent number: 8327228
    Abstract: Methods and apparatus relating to home agent data and memory management are described. In one embodiment, a scrubber logic corrects an error at a location in a memory corresponding to a target address by writing back the corrected version of data to the target location. In an embodiment, a map out logic maps out an index or way of a directory cache in response to a number of errors, corresponding to the directory cache, exceeding a threshold value. Other embodiments are also disclosed.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: December 4, 2012
    Assignee: Intel Corporation
    Inventors: Ganesh Kumar, Dheemanth Nagaraj, Vincent R. Freytag, Eric Delano, Gregory S. Averill
  • HOME AGENT DATA AND MEMORY MANAGEMENT
    Publication number: 20110078492
    Abstract: Methods and apparatus relating to home agent data and memory management are described. In one embodiment, a scrubber logic corrects an error at a location in a memory corresponding to a target address by writing back the corrected version of data to the target location. In an embodiment, a map out logic maps out an index or way of a directory cache in response to a number of errors, corresponding to the directory cache, exceeding a threshold value. Other embodiments are also disclosed.
    Type: Application
    Filed: September 30, 2009
    Publication date: March 31, 2011
    Inventors: Ganesh Kumar, Dheemanth Nagaraj, Vincent R. Freytag, Eric Delano, Gregory S. Averill
  • MEMORY MIRRORING AND MIGRATION AT HOME AGENT
    Publication number: 20110078384
    Abstract: Methods and apparatus relating to memory mirroring and migration at a Home Agent (HA) are described. In one embodiment, a home agent may mirror its data at a slave agent. In some embodiments, a bit in a directory may indicate status of cache lines. Other embodiments are also disclosed.
    Type: Application
    Filed: September 30, 2009
    Publication date: March 31, 2011
    Inventors: Ganesh Kumar, Dheemanth Nagaraj, Vincent R. Freytag, Eric Delano, Gregory S. Averill
  • Controllably Exiting An Unknown State Of A Cache Coherency Directory
    Publication number: 20100332767
    Abstract: In one embodiment, a method includes receiving a read request from a first caching agent and if a directory entry associated with the request is in an unknown state, an invalidating snoop message is sent to at least one other caching agent to invalidate information in a cache location of the other caching agent corresponding to the location of the read request, to enable setting of the directory entry into a known state. Other embodiments are described and claimed.
    Type: Application
    Filed: June 26, 2009
    Publication date: December 30, 2010
    Inventors: Ganesh Kumar, Dheemanth Nagaraj, Vincent R. Freytag, Eric Delano, Gregory S. Averill
  • Bus interface adapted to coalesce snoop responses
    Patent number: 7783843
    Abstract: In a bus interface adapted for usage in a multiple-core processor, an interface couples a bus to the one or more processor cores. The bus interface comprises a queue coupled to the interface which is adapted to receive snoop responses from the processor cores and coalesce snoop responses from the processor cores into a single snoop response that reflects snoop responses from all processor cores.
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: August 24, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Vincent R. Freytag