Patents by Inventor Vincent Rabary
Vincent Rabary has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11632091Abstract: A differential pair for an input stage includes two identical branches in parallel, each branch including a first MOS transistor and a second MOS transistor arranged in series, wherein the first transistor and the second transistor have a channel of the same type, and wherein each of the first transistor and the second transistor has a gate coupled to the same corresponding input of the differential pair and a circuit configured to apply to each of the first transistors a potential difference between a source and a channel-forming region of the first transistor.Type: GrantFiled: August 12, 2021Date of Patent: April 18, 2023Assignee: STMICROELECTRONICS (GRENOBLE 2) SASInventors: Philippe Pignolo, Pawel Fiedorow, Vincent Rabary
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Patent number: 11611321Abstract: The present disclosure relates to an electronic device comprising a pair of first transistors, each first transistor being coupled to a first node by a conduction terminal, a pair of second transistors, each second transistor being coupled to a second node by a conduction terminal, and a third transistor coupling the first and second nodes, the control terminal of the third transistor being coupled to the output of an operational amplifier, the operational amplifier being coupled, at its input, to the first node and to a node of application of a reference voltage.Type: GrantFiled: August 17, 2021Date of Patent: March 21, 2023Assignee: STMicroelectronics (Grenoble 2) SASInventors: Philippe Pignolo, Vincent Rabary
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Publication number: 20220077831Abstract: In an embodiment a differential pair for an input stage includes two identical branches in parallel, each branch including a first MOS transistor and a second MOS transistor arranged in series, wherein the first transistor and the second transistor have a channel of the same type, and wherein each of the first transistor and the second transistor has a gate coupled to the same corresponding input of the differential pair and a circuit configured to apply to each of the first transistors a potential difference between a source and a channel-forming region of the first transistor.Type: ApplicationFiled: August 12, 2021Publication date: March 10, 2022Inventors: Philippe Pignolo, Pawel Fiedorow, Vincent Rabary
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Publication number: 20220069790Abstract: The present disclosure relates to an electronic device comprising a pair of first transistors, each first transistor being coupled to a first node by a conduction terminal, a pair of second transistors, each second transistor being coupled to a second node by a conduction terminal, and a third transistor coupling the first and second nodes, the control terminal of the third transistor being coupled to the output of an operational amplifier, the operational amplifier being coupled, at its input, to the first node and to a node of application of a reference voltage.Type: ApplicationFiled: August 17, 2021Publication date: March 3, 2022Inventors: Philippe Pignolo, Vincent Rabary
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Patent number: 9460789Abstract: A non-volatile digital memory includes: a plurality of thin film resistors; and a control circuit adapted to: program, during a first programming phase, the thin film resistors with a plurality of bits of data by passing a current through at least one of the thin film resistors to reduce its resistance; and read, during a restoration phase, the plurality of bits of data stored by the thin film resistors by generating an electrical signal associated with each thin film resistor and comparing each electrical signal with a reference signal.Type: GrantFiled: March 2, 2015Date of Patent: October 4, 2016Assignee: STMicroelectronics (Grenoble 2) SASInventors: Vincent Rabary, Nicolas Aupetit
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Publication number: 20150248934Abstract: A non-volatile digital memory includes: a plurality of thin film resistors; and a control circuit adapted to: program, during a first programming phase, the thin film resistors with a plurality of bits of data by passing a current through at least one of the thin film resistors to reduce its resistance; and read, during a restoration phase, the plurality of bits of data stored by the thin film resistors by generating an electrical signal associated with each thin film resistor and comparing each electrical signal with a reference signal.Type: ApplicationFiled: March 2, 2015Publication date: September 3, 2015Inventors: Vincent Rabary, Nicolas Aupetit
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Patent number: 8487704Abstract: A method generates a reference voltage by steps including: generating a reference signal from a voltage source; generating a comparison signal of the reference signal with a voltage reference; sampling the comparison signal; adjusting a numerical value as a function of the result of the comparison and of the numerical value; and converting the current numerical value into a voltage corresponding to the reference voltage.Type: GrantFiled: September 8, 2011Date of Patent: July 16, 2013Assignee: STMicroelectronics (Grenoble 2) SASInventors: Vincent Rabary, Frédéric Goutti, Robert Cittadini, Alexandre Huffenus, Gael Pillonnet
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Publication number: 20120126892Abstract: A method generates a reference voltage by steps including: generating a reference signal from a voltage source; generating a comparison signal of the reference signal with a voltage reference; sampling the comparison signal; adjusting a numerical value as a function of the result of the comparison and of the numerical value; and converting the current numerical value into a voltage corresponding to the reference voltage.Type: ApplicationFiled: September 8, 2011Publication date: May 24, 2012Applicant: STMICROELECTRONICS (GRENOBLE 2) SASInventors: Vincent Rabary, Frédéric Goutti, Robert Cittadini, Alexandre Huffenus, Gael Pillonnet
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Patent number: 8054130Abstract: A method and corresponding circuit that adjusts the gain of an audio output stage having a class D amplifier, this method including the steps of setting the gain to a nominal value, analyzing an output signal during successive clock periods, counting the number of clock periods during which the signal is in a state corresponding to a saturation, decreasing the gain if the number reaches, before the end of a first time interval, a value corresponding to a first percentage, maintaining the gain constant if, at the end of a second time interval, different from the first interval, the number corresponds to a second percentage being comprised between the first percentage and a third percentage, and increasing the gain if, at the end of the second time interval, the number corresponds to a fourth percentage, lower than the third percentage.Type: GrantFiled: March 31, 2010Date of Patent: November 8, 2011Assignee: STMicroelectronics (Grenoble 2) SASInventors: Vincent Rabary, Robert Cittadini, Alexandre Huffenus, Gaël Pillonnet
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Publication number: 20100253429Abstract: A method and corresponding circuit that adjusts the gain of an audio output stage having a class D amplifier, this method including the steps of setting the gain to a nominal value, analyzing an output signal during successive clock periods, counting the number of clock periods during which the signal is in a state corresponding to a saturation, decreasing the gain if the number reaches, before the end of a first time interval, a value corresponding to a first percentage, maintaining the gain constant if, at the end of a second time interval, different from the first interval, the number corresponds to a second percentage being comprised between the first percentage and a third percentage, and increasing the gain if, at the end of the second time interval, the number corresponds to a fourth percentage, lower than the third percentage.Type: ApplicationFiled: March 31, 2010Publication date: October 7, 2010Applicant: STMICROELECTRONICS (GRENOBLE 2) SASInventors: Vincent Rabary, Robert Cittadini, Alexandre Huffenus, Gaël Pillonnet
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Patent number: 7113031Abstract: A power amplifier circuit comprising at least one first amplifier having a first input receiving an input voltage through at least one first coupling capacitor and connected to an output of the first amplifier, and having a second input, separate from the first input, receiving a reference voltage supplied by a time constant circuit comprising a decoupling capacitor, at least one first controllable switch connecting the first and second inputs.Type: GrantFiled: April 1, 2004Date of Patent: September 26, 2006Assignee: STMicroelectronics S.A.Inventors: Vincent Rabary, Frédéric Goutti
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Publication number: 20040196099Abstract: A power amplifier circuit comprising at least one first amplifier having a first input receiving an input voltage through at least one first coupling capacitor and connected to an output of the first amplifier, and having a second input, separate from the first input, receiving a reference voltage supplied by a time constant circuit comprising a decoupling capacitor, at least one first controllable switch connecting the first and second inputs.Type: ApplicationFiled: April 1, 2004Publication date: October 7, 2004Inventors: Vincent Rabary, Frederic Goutti
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Patent number: 6774726Abstract: An amplifier including first, second, and third series-connected stages, the third stage including a MOS output transistor having its source or drain forming an output terminal of the amplifier, including means for detecting the transition from a first operating state of the output transistor in which the drain current varies little with the voltage between the drain and the source to a second state in which the drain current varies substantially proportionally to the voltage between the drain and the source; and means for, upon detection of such a transition, having the voltage gain of the amplifier and/or the product between the bandwidth of the amplifier and the voltage gain of the amplifier at the upper limit frequency of the bandwidth drop.Type: GrantFiled: December 17, 2002Date of Patent: August 10, 2004Assignee: STMicroelectronics S.A.Inventors: Frédéric Goutti, Vincent Rabary
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Publication number: 20030112077Abstract: An amplifier including first, second, and third series-connected stages, the third stage including a MOS output transistor having its source or drain forming an output terminal of the amplifier, including means for detecting the transition from a first operating state of the output transistor in which the drain current varies little with the voltage between the drain and the source to a second state in which the drain current varies substantially proportionally to the voltage between the drain and the source; and means for, upon detection of such a transition, having the voltage gain of the amplifier and/or the product between the bandwidth of the amplifier and the voltage gain of the amplifier at the upper limit frequency of the bandwidth drop.Type: ApplicationFiled: December 17, 2002Publication date: June 19, 2003Applicant: STMicroelectronics S.A.Inventors: Frederic Goutti, Vincent Rabary