Patents by Inventor Vincent RAY

Vincent RAY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250209002
    Abstract: A processor comprising multiple cores, each including a local cache; multiple memory banks forming a shared memory for the multiple cores; a directory-based cache coherence protocol manager, comprising for each core a circuit for consolidating multiple cache line invalidation commands received from the different memory banks. The consolidation circuit comprises a counter for counting the received invalidation commands; and a selection circuit configured to, depending on whether the count of received invalidation commands is equal to 1 or greater, transmit to the cache the single received invalidation command or a consolidated invalidation command for the cache lines identified in the received invalidation commands, in a format usable by the cache to simultaneously invalidate the identified cache lines.
    Type: Application
    Filed: December 20, 2024
    Publication date: June 26, 2025
    Inventor: Vincent RAY
  • Publication number: 20210200904
    Abstract: A processor having a plurality of protection rings and comprising a protection ring management system in which the attributions of exceptions or privileged resources to protection rings are defined by a programmable table.
    Type: Application
    Filed: December 31, 2020
    Publication date: July 1, 2021
    Inventors: Pierre GUIRONNET DE MASSAS, Vincent RAY, Benoit DUPONT DE DINECHIN
  • Publication number: 20170255571
    Abstract: The invention relates to a method for updating a variable shared between multiple processor cores. The following steps are implemented during execution in one of the cores of a local scope atomic read-modify-write instruction (AFA), having a memory address (a1) of the shared variable as a parameter: performing operations of the atomic instruction in a cache line (L(a1)) allocated to the memory address; and locally locking the cache line (LCK) while authorizing access to the shared variable by cores connected to another cache memory of same level during execution of the local scope atomic instruction.
    Type: Application
    Filed: March 7, 2017
    Publication date: September 7, 2017
    Applicant: KALRAY
    Inventors: Benoit DUPONT DE DINECHIN, Marta RYBCZYNSKA, Vincent RAY
  • Publication number: 20170192792
    Abstract: A processor including multiple processing units for processing multiple elementary instructions in parallel, the elementary instructions including one or more syllables, each having a rank in the elementary instruction, and an input circuit configured to receive an instruction bundle including multiple elementary instructions, and to transmit to the processing units all syllables of first rank of the elementary instructions of the instruction bundle before syllables of second rank of the elementary instructions of the instruction bundle, the syllables of same rank being ordered according to the target processing unit of each syllable.
    Type: Application
    Filed: April 27, 2015
    Publication date: July 6, 2017
    Applicant: KALRAY
    Inventors: Renaud AYRIGNAC, Vincent RAY, Benoît DUPONT DE DINECHIN
  • Publication number: 20150339256
    Abstract: An inter-processor synchronization method using point-to-point links, comprises the steps of defining a point-to-point synchronization channel between a source processor and a target processor; executing in the source processor a wait command expecting a notification associated with the synchronization channel, wherein the wait command is designed to stop the source processor until the notification is received; executing in the target processor a notification command designed to transmit through the point-to-point link the notification expected by the source processor; executing in the target processor a wait command expecting a notification associated with the synchronization channel, wherein the wait command is designed to stop the target processor until the notification is received; and executing in the source processor a notification command designed to transmit through the point-to-point link the notification expected by the target processor.
    Type: Application
    Filed: May 19, 2015
    Publication date: November 26, 2015
    Inventors: Benoît DUPONT DE DINECHIN, Vincent RAY