Abstract: An assessment method comprising: using an assessment apparatus to generate assessment signals representing a property of a surface of a sample; processing the assessment signals to identify candidate defects and outputting a candidate defect signal; monitoring the status of the assessment apparatus for error conditions and generating a status signal indicating any error conditions during functioning of the assessment apparatus; and analysing the candidate defect signal to determine if the candidate defects are real defects; wherein analysis of a candidate defect is not completed if the status signal indicates that the assessment signal(s) and/or the candidate defect signal corresponding to the candidate defect would have been affected by an error condition.

Abstract: The embodiments of the present disclosure provide a method of processing data derived from a sample, comprising processing an initial data set of elements derived from a detection by a detector for calibration, the data set comprising elements representing nuisance signals and detection signals. The processing of the initial data set comprising: fitting a distribution model to the initial data set to create a nuisance distribution model; setting a signal strength value, and selecting elements in the initial data set having a magnitude greater than the signal strength value as a set of defect candidates; fitting a distribution model to the set of defect candidates to create a defect distribution model of detection signals; and determining a signal strength threshold dependent on at least the defect distribution model. The determining comprising correcting the defect distribution model.

Abstract: Methods of processing a sample and charged particle assessment systems are disclosed. In one arrangement, a sample is processed using a multi-beam of sub-beams of charged particles. At least a portion of a sub-beam processable area is processed with each sub-beam. The sub-beam processable area comprising an array of sections having rows of sections and columns of sections. Each row of sections defines an elongate region that is substantially equal to or smaller than a pitch at the sample surface of the sub-beams in the multi-beam. A plurality of the sections are processed.

Abstract: A charged particle assessment apparatus comprising: a charged particle beam device; an actuated sample stage; a hot component and a thermal compensator. The actuated sample stage is configured to hold a sample. The hot component is configured to operate such that, during operation, heat is radiated toward a sample held on the sample holder. The hot component is smaller than the sample. The thermal compensator is configured to heat the sample so as to reduce thermal gradients therein.

Abstract: A data processing device for detecting defects in sample images generated by a charged particle assessment system, the device comprising: an input module, a filter module, a reference image module and a comparator. The input module is configured to receive a sample image from the charged particle assessment system. The filter module is configured to apply a filter to the sample image to generate a filtered sample image. The reference image module is configured to provide a reference image based on one or more source images. The comparator is configured to compare the filtered sample image to the reference image so as to detect defects in the sample image.

Abstract: An electronic device comprising a semiconductor chip which comprises a plurality of structures formed in the semiconductor chip, wherein the semiconductor chip is a member of a set of semiconductor chips, the set of semiconductor chips comprises a plurality of subsets of semiconductor chips, and the semiconductor chip is a member of only one of the subsets. The plurality of structures of the semiconductor chip includes a set of common structures which is the same for all of the semiconductor chips of the set, and a set of non-common structures, wherein the non-common structures of the semiconductor chip of the subset is different from a non-common circuit of the semiconductor chips in every other subset. At least a first portion of the non-common structures and a first portion of the common structures form a first non-common circuit, wherein the first non-common circuit of the semiconductor chips of each subset is different from a non-common circuit of the semiconductor chips in every other subset.

Abstract: The present invention concerns a method of determining alignment of electron optical components in a charged particle apparatus. The charged particle apparatus comprising: an aperture array and a detector configured to detect charged particles corresponding to beamlets that pass through the corresponding apertures in the aperture array. The method comprises: scanning each beamlet in a plane of the aperture array over a portion of the aperture array in which a corresponding aperture of the aperture array is defined so that charged particles of each beamlet may pass through the corresponding aperture; detecting during the scan any charged particles corresponding to each beamlet that passes through the corresponding aperture; generating a detection pixel for each beamlet based on the detection of charged particles corresponding to each beamlet at intervals of the scan; and collecting information comprised in the detection pixel such as the intensity of charged particles.

Abstract: An electronic device comprising a semiconductor chip which comprises a plurality of structures formed in the semiconductor chip, wherein the semiconductor chip is a member of a set of semiconductor chips, the set of semiconductor chips comprises a plurality of subsets of semiconductor chips, and the semiconductor chip is a member of only one of the subsets. The plurality of structures of the semiconductor chip includes a set of common structures which is the same for all of the semiconductor chips of the set, and a set of non-common structures, wherein the non-common structures of the semiconductor chip of the subset is different from a non-common circuit of the semiconductor chips in every other subset. At least a first portion of the non-common structures and a first portion of the common structures form a first non-common circuit, wherein the first non-common circuit of the semiconductor chips of each subset is different from a non-common circuit of the semiconductor chips in every other subset.

Abstract: A data processing device for detecting defects in sample image data generated by a charged particle assessment system, the device comprising: a first processing module configured to receive a sample image datastream from the charged particle assessment system, the sample image datastream comprising an ordered series of data points representing an image of the sample, and to apply a first defect detection test to select a subset of the sample image datastream as first selected data, wherein the first defect detection test is a localised test which is performed in parallel with receipt of the sample image datastream; and a second processing module configured to receive the first selected data and to apply a second defect detection test to select a subset of the first selected data as second selected data.

Abstract: A method of creating electronic devices such as semiconductor chips using a maskless lithographic exposure system such as a charged particle multi-beamlet lithography system (301A-301D). The maskless lithographic exposure system comprises a lithography subsystem (316) including a maskless pattern writer such as a charged particle multi-beamlet lithography machine (1) or ebeam machine. The method comprises introducing unique chip design data (430) or information related thereto into pattern data comprising common chip design data before streaming the pattern data to the maskless pattern writer.

Abstract: Method of manufacturing electronic devices using a maskless lithographic exposure system using a maskless pattern writer. The method comprises generating beamlet control data for controlling the maskless pattern writer to expose a wafer for creation of the electronic devices, wherein the beamlet control data is generated based on a feature data set defining features selectable for individualizing the electronic devices, wherein exposure of the wafer according to the beamlet control data results in exposing a pattern having a different selection of the features from the feature data set for different subsets of the electronic devices.

Abstract: A method of creating electronic devices such as semiconductor chips using a maskless lithographic exposure system such as a charged particle multi-beamlet lithography system (301A-301D). The maskless lithographic exposure system comprises a lithography subsystem (316) including a maskless pattern writer such as a charged particle multi-beamlet lithography machine (1) or ebeam machine. The method comprises introducing unique chip design data (430) or information related thereto into pattern data comprising common chip design data before streaming the pattern data to the maskless pattern writer.

Abstract: An electronic device comprising a semiconductor chip which comprises a plurality of structures formed in the semiconductor chip, wherein the semiconductor chip is a member of a set of semiconductor chips, the set of semiconductor chips comprises a plurality of subsets of semiconductor chips, and the semiconductor chip is a member of only one of the subsets. The plurality of structures of the semiconductor chip includes a set of common structures which is the same for all of the semiconductor chips of the set, and a set of non-common structures, wherein the non-common structures of the semiconductor chip of the subset is different from a non-common circuit of the semiconductor chips in every other subset. At least a first portion of the non-common structures and a first portion of the common structures form a first non-common circuit, wherein the first non-common circuit of the semiconductor chips of each subset is different from a non-common circuit of the semiconductor chips in every other subset.

Abstract: An electronic device comprising a semiconductor chip which comprises a plurality of structures formed in the semiconductor chip, wherein the semiconductor chip is a member of a set of semiconductor chips, the set of semiconductor chips comprises a plurality of subsets of semiconductor chips, and the semiconductor chip is a member of only one of the subsets. The plurality of structures of the semiconductor chip includes a set of common structures which is the same for all of the semiconductor chips of the set, and a set of non-common structures, wherein the non-common structures of the semiconductor chip of the subset is different from a non-common circuit of the semiconductor chips in every other subset. At least a first portion of the non-common structures and a first portion of the common structures form a first non-common circuit, wherein the first non--common circuit of the semiconductor chips of each subset is different from a non-common circuit of the semiconductor chips in every other subset.

Abstract: An electronic device comprising a semiconductor chip which comprises a plurality of structures formed in the semiconductor chip, wherein the semiconductor chip is a member of a set of semiconductor chips, the set of semiconductor chips comprises a plurality of subsets of semiconductor chips, and the semiconductor chip is a member of only one of the subsets. The plurality of structures of the semiconductor chip includes a set of common structures which is the same for all of the semiconductor chips of the set, and a set of non-common structures, wherein the non-common structures of the semiconductor chip of the subset is different from a non-common circuit of the semiconductor chips in every other subset. At least a first portion of the non-common structures and a first portion of the common structures form a first non-common circuit, wherein the first non-common circuit of the semiconductor chips of each subset is different from a non-common circuit of the semiconductor chips in every other subset.

Abstract: An electronic device comprising a semiconductor chip which comprises a plurality of structures formed in the semiconductor chip, wherein the semiconductor chip is a member of a set of semiconductor chips, the set of semiconductor chips comprises a plurality of subsets of semiconductor chips, and the semiconductor chip is a member of only one of the subsets. The plurality of structures of the semiconductor chip includes a set of common structures which is the same for all of the semiconductor chips of the set, and a set of non-common structures, wherein the non-common structures of the semiconductor chip of the subset is different from a non-common circuit of the semiconductor chips in every other subset. At least a first portion of the non-common structures and a first portion of the common structures form a first non-common circuit, wherein the first non-common circuit of the semiconductor chips of each subset is different from a non-common circuit of the semiconductor chips in every other subset.

Abstract: Method of manufacturing electronic devices using a maskless lithographic exposure system using a maskless pattern writer. The method comprises generating beamlet control data for controlling the maskless pattern writer to expose a wafer for creation of the electronic devices, wherein the beamlet control data is generated based on a feature data set defining features selectable for individualizing the electronic devices, wherein exposure of the wafer according to the beamlet control data results in exposing a pattern having a different selection of the features from the feature data set for different subsets of the electronic devices.

Abstract: An apparatus for transferring a target, such as a substrate or a substrate support structure onto which a substrate has been clamped, from a substrate transfer system to a vacuum chamber of a lithography system. The apparatus comprises a load lock chamber for transferring the target into and out of the vacuum chamber. The load lock chamber comprises a first wall with a first passage providing access between a robot space and the interior of the load lock chamber, a second wall with a second passage providing access between the interior of the load lock chamber and the vacuum chamber, and plurality of handling robots for transferring the targets comprising: a first handling robot movable within the robot space to access the substrate transfer system and the first passage; and a second handling robot movable within the load lock chamber to access the first passage and the second passage.

Abstract: A multi-beamlet charged particle beamlet lithography system for transferring a pattern to a surface of a substrate. The system comprises a projection system (311) for projecting a plurality of charged particle beamlets (7) onto the surface of the substrate; a chuck (313) moveable with respect to the projection system; a beamlet measurement sensor (i.a. i.e., 505, 511) for determining one or more characteristics of one or more of the charged particle beamlets, the beamlet measurement sensor having a surface (501) for receiving one or more of the charged particle beamlets; and a position mark measurement system for measuring a position of a position mark (610, 620, 635), the position mark measurement system comprising an alignment sensor (361, 362). The chuck comprises a substrate support portion for supporting the substrate, a beamlet measurement sensor portion (460) for accommodating the surface of the beamlet measurement sensor, and a position mark portion (470) for accommodating the position mark.

Abstract: A sub-beam aperture array for forming a plurality of sub-beams from one or more charged particle beams. The sub-beam aperture array comprises one or more beam areas, each beam area comprising a plurality of sub-beam apertures arranged in a non-regular hexagonal pattern, the sub-beam apertures arranged so that, when projected in a first direction onto a line parallel to a second direction, the sub-beam apertures are uniformly spaced along the line, and wherein the first direction is different from the second direction. The system further comprises a beamlet aperture array with a plurality of beamlet apertures arranged in one or more groups. The beamlet aperture array is arranged to receive the sub-beams and form a plurality of beamlets at the locations of the beamlet apertures of the beamlet array.