Patents by Inventor Vincent Telandro

Vincent Telandro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7375502
    Abstract: A method and a circuit for scrambling the current signature of a load comprising at least one integrated circuit executing digital processings, including supplying at least the integrated circuit from a supply voltage external to the circuit by combining a current provided by a first linear regulator with a current provided by at least one capacitive switched-mode power supply circuit with one or several switched capacitances.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: May 20, 2008
    Assignees: STMicroelectronics S.A., Universite D.Aix-Marseille I
    Inventors: Alexandre Malherbe, Edith Kussener, Vincent Telandro
  • Patent number: 7365523
    Abstract: A method and a circuit for scrambling the current signature of a load including at least one integrated circuit executing digital processings, including the step of, at least on the load ground side, combining a current absorbed by a first linear regulator with a current absorbed by at least one capacitive switched-mode circuit with one or several switched capacitances.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: April 29, 2008
    Assignee: STMicroelectronics S.A.
    Inventors: Alexandre Malherbe, Edith Kussener, Vincent Telandro
  • Publication number: 20060279366
    Abstract: A method and a circuit for generating a pseudo-random digital flow comprising an oscillator, the biasing of which is controllable by an analog bias source controlled by a signal with continuous amplitude and time variatons.
    Type: Application
    Filed: May 25, 2006
    Publication date: December 14, 2006
    Inventors: Edith Kussener, Vincent Telandro, Fabien Chaillan
  • Publication number: 20060176032
    Abstract: A method and a circuit for scrambling the current signature of a load comprising at least one integrated circuit executing digital processings, including supplying at least the integrated circuit from a supply voltage external to the circuit by combining a current provided by a first linear regulator with a current provided by at least one capacitive switched-mode power supply circuit with one or several switched capacitances.
    Type: Application
    Filed: February 7, 2006
    Publication date: August 10, 2006
    Applicants: STMicroelectronics S.A., Universite D'Aix-Marseille I
    Inventors: Alexandre Malherbe, Edith Kussener, Vincent Telandro
  • Publication number: 20060176033
    Abstract: A method and a circuit for scrambling the current signature of a load including at least one integrated circuit executing digital processings, including the step of, at least on the load ground side, combining a current absorbed by a first linear regulator with a current absorbed by at least one capacitive switched-mode circuit with one or several switched capacitances.
    Type: Application
    Filed: February 7, 2006
    Publication date: August 10, 2006
    Applicants: STMicroelectronics S.A., Universite D'Aix-Marseille I
    Inventors: Alexandre Malherbe, Edith Kussener, Vincent Telandro